| 1993 | NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan |
| 1993 | Fault-Tolerant Arbitration in Multichip Crossbar Switches. | Joydeep Ghosh, Nari Krishnamurthy |
| 1993 | Via Minimization in Channel Routing by Layout Modification. | Sandip Das, Bhargab B. Bhattacharya |
| 1993 | A Simplified High Speed Parallel Input Convolver. | Luigi Dadda |
| 1993 | A Hierarchical Test Generation Using High Level Primitives. | Didier Crestani, A. Aguila, L. Eudeline, M.-H. Gentil, Christian Durante |
| 1993 | Towards a Symbolic Logic Minimization Algorithm. | Olivier Coudert, Jean Christophe Madre |
| 1993 | A Provably Good Algorithm for | Jason Cong, Moazzem Hossain, Naveed A. Sherwani |
| 1993 | Synthesis of Self-Checking Sequential Machines Using Cellular Automata. | Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri |
| 1993 | Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. | Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu |
| 1993 | New CMOS Structures for the Synthesis of Dominant Functions. | Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli |
| 1993 | Design of an On-Line Euclidean Processor. | Rachid Bouraoui, Alain Guyot, G. Walker |
| 1993 | MIPS-Driven Early Design and Analysis of VLSI CPU Chips. | Pradip Bose, John-David Wellman |
| 1993 | A Path Delay Fault Simulator for Sequential Circuits. | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
| 1993 | On Optimum Cell Models for Over-the-Cell Routing. | Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani |
| 1993 | Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. | Sandeep Bhatia, Niraj K. Jha |
| 1993 | A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. | Yves Bertrand, Frdric Bancel, Michel Renovell |
| 1993 | FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits. | Bernd Becker, Rolf Krieger |
| 1993 | A Parallel VLSI Circuit Layout Methodology. | S. Bapat, James P. Cohoon |
| 1993 | A Massively Parallel, Micro-Grained VLSI Architecture. | Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin |
| 1993 | Modular Design Methodologies for Image Processing Architectures. | Anna Antola, Alberto Avai, Luca Breveglieri, Andrea Paparella |
| 1993 | Use of Storage Elements as Primitives for Modelling Faults in Synchronous Sequential Circuits. | W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana |
| 1993 | High Level Design Experiences with IDEAS. | C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer |
| 1993 | FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview. | Suhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan |
| 1993 | LATCHECK: A Latchup Checker for VLSI Layouts. | Aditya Agrawal, P. V. Srinivas, Gade Sreenivas, Uttiya Dasgupta |
| 1992 | A Global Test Point Placement Algorithm of Combinational Circuits. | Dong Xiang, Daozheng Wei, Shisong Chen |