| 2009 | Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. | Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram |
| 2009 | Efficient Placement of Compressed Code for Parallel Decompression. | Xiaoke Qin, Prabhat Mishra |
| 2009 | Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. | Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala |
| 2009 | Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel. | Shashank Prasad, Anuj Kumar |
| 2009 | Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. | Almitra Pradhan, Ranga Vemuri |
| 2009 | The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. | Irith Pomeranz, Sudhakar M. Reddy |
| 2009 | A General Approach to High-Level Energy and Performance Estimation in SoCs. | Sandro Penolazzi, Ahmed Hemani, Luca Bolognino |
| 2009 | Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. | Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi |
| 2009 | Systematic Methodology for High-Level Performance Modeling of Analog Systems. | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
| 2009 | Synthesis & Testing for Low Power. | Ajit Pal, Santanu Chattopadhyay |
| 2009 | Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback. | Muhammad Mudassar Nisar, Abhijit Chatterjee |
| 2009 | Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. | K. C. Narasimhamurthy, Roy P. Paily |
| 2009 | Defect Aware to Power Conscious Tests - The New DFT Landscape. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2009 | High-Speed On-Chip Event Counters for Embedded Systems. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2009 | Unified Challenges in Nano-CMOS High-Level Synthesis. | Saraju P. Mohanty |
| 2009 | Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. | Prabhat Mishra, Mingsong Chen |
| 2009 | Power Reduction Techniques and Flows at RTL and System Level. | Anmol Mathur, Qi Wang |
| 2009 | ReConfigurable Technologies. | Mona Mathur |
| 2009 | A Decade of Platform-Based Design: A look backwards, a look forwards. | Grant Martin |
| 2009 | A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. | Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura |
| 2009 | FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System. | J. Manikandan, B. Venkataramani, V. Avanthi |
| 2009 | An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. | Karthikeyan Lingasubramanian, Sanjukta Bhanja |
| 2009 | Design Optimization and Automation for Secure Cryptographic Circuits. | Kuan Jen Lin, Yi Tang Chiu, Shan Chien Fang |
| 2009 | FPGA Based High Performance Double-Precision Matrix Multiplication. | Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan |
| 2009 | Negative Feedback System and Circuit Design. | Nagendra Krishnapura, Shanthi Pavan |