| 2009 | Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. | V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani |
| 2009 | Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. | R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao |
| 2009 | Design of a Low Power, Variable-Resolution Flash ADC. | Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas |
| 2009 | Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura |
| 2009 | A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6m CMOS. | Theja Tulabandhula, Yujendra Mitikiri |
| 2009 | Robust Circuit Design: Challenges and Solutions. | Saurabh K. Tiwary, Amith Singhee, Vikas Chandra |
| 2009 | Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2009 | Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization. | Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil |
| 2009 | Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. | Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur |
| 2009 | Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. | Tameesh Suri, Aneesh Aggarwal |
| 2009 | A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. | Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy |
| 2009 | Exploring the Limits of Port Reduction in Centralized Register Files. | Sandeep Sirsi, Aneesh Aggarwal |
| 2009 | Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. | Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan |
| 2009 | Computational Lithography - Moore Bang for your Buck. | Vivek Singh |
| 2009 | EDA Made-in-India: Fact or Fiction? | Raman Santhanakrishnan, Yatin Trivedi |
| 2009 | Analog IC Design in Nanometer CMOS Technologies. | Willy M. C. Sansen |
| 2009 | Exploiting Hybrid Analysis in Solving Electrical Networks. | V. Siva Sankar, H. Narayanan, Sachin B. Patkar |
| 2009 | A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. | Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta |
| 2009 | Encoding of Floorplans through Deterministic Perturbation. | Debasri Saha, Susmita Sur-Kolay |
| 2009 | H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors. | Sourav Roy |
| 2009 | Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits. | Jaime Ramrez-Angulo, Ramn Gonzlez Carvajal, Antonio J. Lpez-Martn |
| 2009 | 100KHz-20MHz Programmable Subthreshold G | S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya |
| 2009 | Cone Resynthesis ECO Methodology for Multi-Million Gate Designs. | Suresh Raman, Mike Lubyanitsky |
| 2009 | Efficient Analog/RF Layout Closure with Compaction Based Legalization. | Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala |
| 2009 | Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips. | Amir-Mohammad Rahmani, I. Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, Saeed Safari |