| 2010 | On Electrical Modeling of Imperfect Diffusion Patterning. | Tuck-Boon Chan, Puneet Gupta |
| 2010 | Towards Active-Passive Co-synthesis of Multi-gigaHertz Radio Frequency Circuits. | Ritochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala |
| 2010 | Rethinking Threshold Voltage Assignment in 3D Multicore Designs. | Koushik Chakraborty, Sanghamitra Roy |
| 2010 | RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. | Rajat Subhra Chakraborty, Swarup Bhunia |
| 2010 | Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore. | Krishnendu Chakrabarty |
| 2010 | 23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently. | Kalyan Bhattacharyya |
| 2010 | Synthesizability of 3 Party Formal Specifications-Does My Controller See Enough?. | Ansuman Banerjee |
| 2010 | Instruction Selection in ASIP Synthesis Using Functional Matching. | Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar |
| 2010 | Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs. | Mohammad Arjomand, Hamid Sarbazi-Azad |
| 2010 | A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. | Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla |
| 2010 | On Minimization of Test Application Time for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
| 2010 | Functional Refinement: A Generic Methodology for Managing ESL Abstractions. | Syed Saif Abrar, Aravinda Thimmapuram |
| 2009 | Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. | Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu |
| 2009 | New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. | Boxue Yin, Dong Xiang, Zhen Chen |
| 2009 | WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. | Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar |
| 2009 | A Novel Approach for Improving the Quality of Open Fault Diagnosis. | Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume |
| 2009 | Accelerating Embedded System Design. | |
| 2009 | Solutions for a small car - Made for India and Made in India. | |
| 2009 | Reversible Logic Synthesis with Output Permutation. | Robert Wille, Daniel Groe, Gerhard W. Dueck, Rolf Drechsler |
| 2009 | SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. | Weixun Wang, Prabhat Mishra, Ann Gordon-Ross |
| 2009 | Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels. | Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam |
| 2009 | Soft Error Rates with Inertial and Logical Masking. | Fan Wang, Vishwani D. Agrawal |
| 2009 | A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference. | Sanjay Kumar Wadhwa |
| 2009 | Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. | Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham |
| 2009 | An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. | Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind |