| 2010 | A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. | Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos |
| 2010 | Robust System Design. | Subhasish Mitra |
| 2010 | Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. | Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee |
| 2010 | Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP. | J. Manikandan, B. Venkataramani, M. Bhaskar, K. Ashish, R. Raghul, V. Mathangi |
| 2010 | Channel Optimization for the Design of High Speed I/O links. | Rohan Mandrekar, Yaping Zhou, Sungjun Chun, Anand Haridass, Jinwoo Choi, Nanju Na, Daniel M. Dreps, Roger D. Weekly, Paul Harvey |
| 2010 | Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. | Glenn Leary, Karam S. Chatha |
| 2010 | Front-End Design Flows for Systems on Chip: An Embedded Tutorial. | Anshul Kumar, Preeti Ranjan Panda |
| 2010 | FinFET SRAM Design. | Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj |
| 2010 | A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories. | Sanjeev K. Jain, Krishna Srivastva, Sanjiv Kainth |
| 2010 | A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. | Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik |
| 2010 | Impact of Temperature on Test Quality. | Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti |
| 2010 | Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. | Vinayak Honkote, Baris Taskin |
| 2010 | Coverage Management with Inline Assertions and Formal Test Points. | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
| 2010 | Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. | Gautam Hazari, Madhav P. Desai, G. Srinivas |
| 2010 | An Efficient Design of a Reversible Barrel Shifter. | Irina Hashmi, Hafiz Md. Hasan Babu |
| 2010 | Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. | Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier |
| 2010 | A Hardware Scheduler for Real Time Multiprocessor System on Chip. | Nikhil Gupta, Suman Kalyan Mandal, Javier Malave, Ayan Mandal, Rabi N. Mahapatra |
| 2010 | Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation. | Amlan Ghosh, Rob Franklin, Richard B. Brown |
| 2010 | Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. | Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao, Eric A. M. Klumperink |
| 2010 | Clocking-Based Coplanar Wire Crossing Scheme for QCA. | Rajeswari Devadoss, Kolin Paul, M. Balakrishnan |
| 2010 | High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. | Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe |
| 2010 | On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme. | Tamal Das, Pradip Mandal |
| 2010 | An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. | Samiran DasGupta, Pradip Mandal |
| 2010 | A Unified Solution to Scan Test Volume, Time, and Power Minimization. | Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya |
| 2010 | Electrical Modeling of Lithographic Imperfections. | Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta |