| 2010 | An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. | Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas |
| 2010 | An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling. | Debapriya Sahu, Saravana Ganeshan, Ashish Lachhwani, Rittu Sachdev, B. G. Chandrashekar |
| 2010 | A Unified Approach for IP Protection across Design Phases in a Packaged Chip. | Debasri Saha, Susmita Sur-Kolay |
| 2010 | Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. | Kaushik Roy, Byunghoo Jung, Anand Raghunathan |
| 2010 | Modeling of RF- MEMS BAW Resonator. | Ambarish Roy, Bradley P. Barber, Kanti Prasad |
| 2010 | Optical Lithography Simulation with Focus Variation using Wavelet Transform. | Rance Rodrigues, Sandip Kundu |
| 2010 | Pinpointing Cache Timing Attacks on AES. | Chester Rebeiro, Mainack Mondal, Debdeep Mukhopadhyay |
| 2010 | Video Coding Tools and Their Impact on Compression Engine Architecture. | Ajit Venkat Rao |
| 2010 | High Speed Serial Link Transmitter for 10Gig Ethernet Applications. | Navin K. Ramamoorthy, Jayabharath Reddy M, Vishwanath Muniyappa |
| 2010 | Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer. | Abinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti |
| 2010 | Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting. | Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, Govindarajulu Regeti |
| 2010 | Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. | Leneesh Raghavan, Ting Wu |
| 2010 | Synchronized Generation of Directed Tests Using Satisfiability Solving. | Xiaoke Qin, Mingsong Chen, Prabhat Mishra |
| 2010 | Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. | Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu |
| 2010 | The Dawn of 22nm Era: Design and CAD Challenges. | Ruchir Puri, David S. Kung |
| 2010 | Post Assembly Timing Closure for Multi Million Gate Chips. | Shashank Prasad, Dongzi Liu, Oleg Levitsky, Dave Noice, Shailendra Srivastava |
| 2010 | Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | Output-Dependent Diagnostic Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | Exploring Use of NoC for Reconfigurable Video Coding. | Alpesh Patel, Hemangee K. Kapoor |
| 2010 | RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications. | Shyam Parthasarathy, Amit Ranjan Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh Singh Chauhan, Michael Carroll, Dan Kerr, Ali Tombak, Phil Mason |
| 2010 | Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Processes. | Shyam Parthasarathy, Balaji Swaminathan, Ananth Sundaram, Robert A. Groves |
| 2010 | A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. | Karthick Parashar, Romuald Rocher, Daniel Mnard, Olivier Sentieys |
| 2010 | A Reconfigurable Architecture for Secure Multimedia Delivery. | Amit Pande, Joseph Zambreno |
| 2010 | An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters. | Srikanth Pam, Anirban Krishna Bhattacharya, Siddhartha Mukhopadhyay |
| 2010 | Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |