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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2011A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation.Maheshwar Chandrasekar, Michael S. Hsiao
2011Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring.Srinivasaraman Chandrasekaran, Kunal Desai, Arul Sendhil, William Ng
2011Development of a Micro-mechanical Logic Inverter for Low Frequency MEMS Sensor Interfacing.Subha Chakraborty, T. K. Bhattacharyya
2011Efficient Trace Signal Selection for Post Silicon Validation and Debug.Kanad Basu, Prabhat Mishra
2011Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation.Aritra Banerjee, Vishwanath Natarajan, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan, Soumendu Bhattacharya
2011Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski
2011Self-Immunity Technique to Improve Register File Integrity Against Soft Errors.Hussam Amrouch, Jrg Henkel
2011A Scalable LDPC Decoder on GPU.Kiran Kumar Abburi
2010Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.Yang Zhao, Ryan Sturmer, Krishnendu Chakrabarty, Vamsee K. Pamula
2010Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control.Hao Xu, Wen-Ben Jone, Ranga Vemuri
2010A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods.Ming Xu, Gary Grwal
2010Processor Architecture Design Using 3D Integration Technology.Yuan Xie
2010Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems.Weixun Wang, Prabhat Mishra
20104 GHz 130nm Low Voltage PLL Based on Self Biased Technique.Biju Viswanathan, Vijay Viswam, R. Kulanthaivelu, Joseph J. Vettickatt, S. R. Ramya Nair, Lekshmi S. Chandran
2010Modeling of High Frequency Noise in SOI MOSFETs.Muthubalan Varadharajaperumal, Saurabh Sirohi, Sourabh Khandelwal, Ethirajan Tamilmani, Vaidyananthan Subramanian
2010Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs.Himanshu Thapliyal, Nagarajan Ranganathan
2010A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan
2010Identifying the Bottlenecks to the RF Performance of FinFETs.Vaidyanathan Subramanian, Abdelkarim Mercha, Bertrand Parvais, Morin Dehan, Guido Groeseneken, Willy M. C. Sansen, Stefaan Decoutere
2010An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops.Balaji Srinivasan, Vinay Bhaskar Chandratre
2010A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications.Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar
2010Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
2010A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET.Sudipta Sarkar, Ananda S. Roy, Santanu Mahapatra
2010Safe-ERfair.Arnab Sarkar, Rahul Nanda, Sujoy Ghose, P. P. Chakrabarti
2010Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta
2010A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process.Arunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal
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