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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2007A Neural Net Branch Predictor to Reduce Power.Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell
2007A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures.Balasubramanian Sethuraman, Ranga Vemuri
2007Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.Boyan Semerdjiev, Dimitrios Velenis
2007Modeling and Analysis of Noise Margin in SET Logic.Chaitanya Sathe, Santanu Mahapatra
2007Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta
2007Reasoning about the Trends and Challenges of Engineering Design Automation.Alberto L. Sangiovanni-Vincentelli
2007An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm.Rupak Samanta, Rabi N. Mahapatra
2007AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai
2007Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs.Subir K. Roy, Rubin A. Parekhji
2007A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan
2007Bounded Delay Timing Analysis Using Boolean Satisfiability.Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2007Creating a Culture of Innovation.Wim Roelandts
2007Low Shift and Capture Power Scan Tests.Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti
2007Tutorial T1: Designing Secure SoCs.Srivaths Ravi, Stefan Mangard
2007An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu
2007Tutorial IND1B: Realtime Operating Systems for Embedded Systems Development.Uma Maheswar Rao, Suneel Sinha, Naveen Shenoy
2007Impact of NBTI on FPGAs.Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin
2007A 3-dimensional FEM Based Resistance Extraction.Subramanian Rajagopalan, Shabbir H. Batterywala
2007Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan
2007Application Specific Datapath Extension with Distributed I/O Functional Units.Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2007Functional Broadside Tests with Different Levels of Reachability.Irith Pomeranz, Sudhakar M. Reddy
2007Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.Irith Pomeranz, Sudhakar M. Reddy
2007Energy Driven Application SelfAdaptation.Jorgen Peddersen, Sri Parameswaran
2007On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology.Pradipta Patra, Amit Patra, Debaprasad Kastha
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