| 2007 | A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance. | Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty |
| 2007 | Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. | Parimal Patel |
| 2007 | A Novel Approach to Domino Circuit Synthesis. | Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta |
| 2007 | A Low Power Frequency Multiplication Technique for ZigBee Transciever. | Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur |
| 2007 | Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. | Rohit Pandey, Michael L. Bushnell |
| 2007 | Simulation Based Verification using Temporally Attributed Boolean Logic. | Subrat Kumar Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar |
| 2007 | Nexperia Computing Architecture for Connected Consumer Applications. | J. Augusto de Oliveira |
| 2007 | A Novel CMOS Full Adder. | Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi |
| 2007 | Customization of Register File Banking Architecture for Low Power. | Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda |
| 2007 | Controllability-driven Power Virus Generation for Digital Circuits. | K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula |
| 2007 | Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. | Srinath R. Naidu |
| 2007 | An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function. | Debdeep Mukhopadhyay, Pallavi Joshi, Dipanwita Roy Chowdhury |
| 2007 | Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. | Saraju P. Mohanty, Elias Kougianos |
| 2007 | Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. | Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie |
| 2007 | JouleQuest: An Accurate Power Model for the StarCore DSP Platform. | Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia |
| 2007 | FPGA Implementation of Low Power Parallel Multiplier. | Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar |
| 2007 | 7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer. | Debashis Mandal, T. K. Bhattacharyya |
| 2007 | Statistical Leakage and Timing Optimization for Submicron Process Variation. | Yuanlin Lu, Vishwani D. Agrawal |
| 2007 | Power-Efficient Asynchronous Design. | Yijun Liu, Zhenkun Li, Pinghua Chen, Guangcong Liu |
| 2007 | Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha |
| 2007 | Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin |
| 2007 | Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit. | Gongqiong Li, Zhaolin Li |
| 2007 | A Process Scheduler-Based Approach to NoC Power Management. | Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaky, Rajaraman Ramanarayanan, Balaji Vaidyanathan |
| 2007 | Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. | Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min |
| 2007 | Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. | Kim T. Le, Dong Hyun Baik, Kewal K. Saluja |