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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2006Phase Change Memory Faults.M. Jagadesh Kumar, Ali A. Orouji
2006Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication.Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda
2006A Comprehensive SoC Design Methodology for Nanometer Design Challenges.R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude
2006Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research.Andreas Kuehlmann
2006A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty
2006Exploring Logic Block Granularity in Leakage Tolerant FPGA.Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
2006Reducing Design Verification Cycle Time through Testbench Redundancy.Aman Kokrady, Theo J. Powell, S. Ramakrishnan
2006A Single Supply Level Shifter for Multi-Voltage Systems.Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri
2006Techniques for On-Chip Process Voltage and Temperature Detection and Compensation.Qadeer Ahmad Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa, Kulbhushan Misri
2006Aliasing Analysis of Spectral Statistical Response Compaction Techniques.Omar I. Khan, Michael L. Bushnell
2006Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
2006On the Size and Generation of Minimal N-Detection Tests.Kalyana R. Kantipudi
2006Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
2006CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture.Xin Jia, Ranga Vemuri
2006Carbon Nanotube Electronics.Ali Javey, Hongjie Dai
2006Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil
2006A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology.Sanjeev K. Jain, Pankaj Agarwal
2006Testing High-Speed IO Links Using On-Die Circuitry.Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard
2006Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation.Motoi Ichihashi, Haruki Toda
2006The Technological and Geographical Migration of the Semiconductor Industry.Jackson Hu
2006An Asynchronous Interconnect Architecture for Device Security Enhancement.Simon Hollis, Simon W. Moore
2006A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.Narender Hanchate, Nagarajan Ranganathan
2006Low-Cost Production Testing of Wireless Transmitters.Achintya Halder, Abhijit Chatterjee
2006Efficient Design and Analysis of Robust Power Distribution Meshes.Puneet Gupta, Andrew B. Kahng
2006Generating Scalable Polynomial Models: Key to Low Power High Performance Designs.G. Girishankar, Shitanshu Tiwari
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