| 2005 | A Combinational Logic Mapper for Actel's SX/AX Family. | Santanu Chattopadhyay, Manas Kumar Dewangan |
| 2005 | Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF. | Abhijit Chatterjee, Ali Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay |
| 2005 | Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. | Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney |
| 2005 | Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. | Kameshwar Chandrasekar, Michael S. Hsiao |
| 2005 | Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. | Avik Chakraborty |
| 2005 | Design, Testing, and Applications of Digital Microfluidics-Based Biochips. | Krishnendu Chakrabarty |
| 2005 | A RISC Hardware Platform for Low Power Java. | Paul Capewell, Ian Watson |
| 2005 | A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. | Charlie Brej, Jim D. Garside |
| 2005 | Power-Aware, Reliable Microprocessor Design. | Pradip Bose |
| 2005 | VLSI Design Challenges for Gigascale Integration. | Shekhar Borkar |
| 2005 | Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. | R. D. (Shawn) Blanton, Subhasish Mitra |
| 2005 | A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems. | Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim, Thomas Chen |
| 2005 | Compact MOSFET Models for Low Power Analog CMOS Design. | A. B. Bhattacharyya |
| 2005 | Power Optimization in Current Mode Circuits. | M. S. Bhat, H. S. Jamadagni |
| 2005 | A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. | K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti |
| 2005 | Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. | Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan |
| 2005 | Memory-Centric Motion Estimator. | Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan |
| 2005 | Modeling Usable and Reusable Transactors in System Verilog. | Janick Bergeron |
| 2005 | Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. | Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta |
| 2005 | Variance Reduction in Monte Carlo Capacitance Extraction. | Shabbir H. Batterywala, Madhav P. Desai |
| 2005 | Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. | Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti |
| 2005 | Design Issues in Switched Capacitor Ladder Filters. | Arindam Basu, Anindya Sundar Dhar |
| 2005 | Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. | Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar |
| 2005 | Computer Aided Test (CAT) Tool for Mixed Signal SOCs. | Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury |
| 2005 | A Novel Low Power 16X16 Content Addressable Memory Using PA. | G. Josemin Bala, J. Raja Paul Perinbam |