| 2018 | ISCAS | Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. | Antonio J. Gins, Antonio Lopez-Angulo, Eduardo J. Peralas, Adoracin Rueda |
| 2017 | DATE | On the limits of machine learning-based test: A calibrated mixed-signal system case study. | Manuel J. Barragn, Gildas Lger, Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda |
| 2016 | ETS | Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. | Antonio J. Gins, Eduardo J. Peralas, Gildas Lger, Adoracin Rueda, Guillaume Renaud, Manuel J. Barragn, Salvador Mir |
| 2014 | ETS | INL systematic reduced-test technique for Pipeline ADCs. | Eduardo J. Peralas, Antonio Jose Gins, Adoracin Rueda |
| 2012 | ISCAS | Analysis of steady-state common-mode response in differential LC-VCOs. | Ricardo Doldn, Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda |
| 2010 | DDECS | A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology. | Alberto Villegas, Diego Vzquez, Adoracin Rueda |
| 2010 | ETS | Low-cost signature test of RF blocks based on envelope response analysis. | Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vzquez, Adoracin Rueda, Jos Luis Huertas |
| 2010 | ISCAS | On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. | Antonio J. Gins, Ricardo Doldn, Manuel J. Barragan Asian, Adoracin Rueda, Eduardo J. Peralas |
| 2009 | DDECS | A CMOS bio-impedance measurement system. | Alberto Yufera, Adoracin Rueda |
| 2008 | DATE | Practical Implementation of a Network Analyzer for Analog BIST Applications. | Manuel J. Barragan Asian, Diego Vzquez, Adoracin Rueda |
| 2007 | ISCAS | Improved Background Algorithms for Pipeline ADC Full Calibration. | Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda |
| 2006 | DDECS | A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35m Technology. | Manuel J. Barragan Asian, Diego Vzquez, Adoracin Rueda |
| 2006 | ETS | Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators. | Gildas Lger, Adoracin Rueda |
| 2006 | ISCAS | Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. | Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda |
| 2005 | ISCAS | Full calibration digital techniques for pipeline ADCs. | Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda |
| 2004 | DATE | Digital Background Gain Error Correction in Pipeline ADCs. | Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda |
| 2004 | DATE | A Digital Test for First-Order [Sigma-Delta] Modulators. | Gildas Lger, Adoracin Rueda |
| 2004 | DATE | A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications. | Diego Vzquez, Gildas Lger, Gloria Huertas, Adoracin Rueda, Jos L. Huertas |
| 2002 | DATE | A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. | Antonio J. Gins, Eduardo J. Peralas, Adoracin Rueda, Ralf Seepold, Natividad Martnez Madrid |
| 2002 | ISCAS | High-speed low-power logic gates using floating gates. | Esther Rodrguez-Villegas, Jos M. Quintana, Maria J. Avedillo, Adoracin Rueda |
| 2002 | ISCAS | A micropower log domain FGMOS filter. | Esther Rodrguez-Villegas, Adoracin Rueda, Alberto Yufera |
| 2002 | ISCAS | Practical solutions for the application of the oscillation-based-test in analog integrated circuits. | Diego Vzquez, Gloria Huertas, Gildas Lger, Adoracin Rueda, Jos L. Huertas |
| 2002 | VTS | Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation. | Diego Vzquez, Gloria Huertas, Gildas Lger, Adoracin Rueda, Jos L. Huertas |
| 2001 | DATE | Analog/mixed-signal IP modeling for design reuse. | Natividad Martnez Madrid, Eduardo J. Peralas, Antonio J. Acosta, Adoracin Rueda |
| 2001 | ISCAS | Structural testing of pipelined analog to digital converters. | Eduardo J. Peralas, Adoracin Rueda, Jos L. Huertas |
| 2001 | ISCAS | A 1.25 V FGMOS filter using translinear circuits. | Esther Rodrguez-Villegas, Adoracin Rueda, Alberto Yufera |
| 2001 | VTS | Self-Testable Pipelined ADC with Low Hardware Overhead. | Eduardo J. Peralas, Gloria Huertas, Adoracin Rueda, Jos L. Huertas |
| 2000 | DATE | A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. | Eduardo J. Peralas, Antonio J. Acosta, Adoracin Rueda, Jos L. Huertas |
| 2000 | ISCAS | VHDL-based behavioural description of pipeline ADCs. | Eduardo J. Peralas, Antonio J. Acosta, Adoracin Rueda, Jos L. Huertas |
| 2000 | ISCAS | A low-voltage √x floating-gate MOS integrator. | Esther O. Rodrguez, Alberto Yufera, Adoracin Rueda |
| 2000 | ISCAS | A g | Esther O. Rodrguez, Alberto Yufera, Adoracin Rueda |
| 2000 | VLSID | Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell. | Gloria Huertas, Diego Vzquez, Adoracin Rueda, Jos L. Huertas |
| 1999 | ISCAS | vMOS-based sorters for multiplier implementations. | Esther Rodrguez-Villegas, Maria J. Avedillo, Jos M. Quintana, Gloria Huertas, Adoracin Rueda |
| 1999 | ISCAS | Programmable low-voltage continuous-time filter for audio applications. | Alberto Yufera, Adoracin Rueda |
| 1999 | ITC | Effective oscillation-based test for application to a DTMF filter bank. | Gloria Huertas, Diego Vzquez, Adoracin Rueda, Jos L. Huertas |
| 1998 | DATE | Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. | Salvador Mir, Adoracin Rueda, Diego Vzquez, Jos Luis Huertas |
| 1998 | DATE | An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. | Juan A. Prieto, Adoracin Rueda, Ian Andrew Grout, Eduardo J. Peralas, Jos L. Huertas, Andrew Mark David Richardson |
| 1998 | ITC | DfT and on-line test of high-performance data converters: a practical case. | Eduardo J. Peralas, Adoracin Rueda, Juan A. Prieto, Jos L. Huertas |
| 1997 | DAC | SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. | Salvador Mir, Adoracin Rueda, Thomas Olbrich, Eduardo J. Peralas, Jos Luis Huertas |
| 1997 | DATE | A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. | Juan A. Prieto, Adoracin Rueda, Jos M. Quintana, Jos Luis Huertas |
| 1997 | ITC | Analog and Mixed-Signal Benchmark Circuits-First Release. | Bozena Kaminska, Karim Arabi, I. Bell, Jos L. Huertas, Bruce C. Kim, Adoracin Rueda, Mani Soma, Prashant Goteti |
| 1997 | VTS | A DFT Technique for Analog-to-Digital Converters with digital correction. | Eduardo J. Peralas, Adoracin Rueda, Jos L. Huertas |
| 1996 | VTS | Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. | Diego Vzquez, Jos L. Huertas, Adoracin Rueda |
| 1995 | ICCAD | Statistical behavioral modeling and characterization of A/D converters. | Eduardo J. Peralas, Adoracin Rueda, Jos Luis Huertas |
| 1995 | VTS | A solution for the on-line test of analog ladder filters. | Diego Vzquez, Adoracin Rueda, Jos L. Huertas |
| 1994 | ISCAS | An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. | Juan A. Prieto, Jos M. Quintana, Adoracin Rueda, Jos L. Huertas |
| 1994 | ISCAS | A Low-Cost Strategy for Testing Analog Filters. | Diego Vzquez, Adoracin Rueda, Jos L. Huertas |
| 1994 | ISCAS | A Study of the Sensitivity of Switched-Current Wave Analog Filters to Mismatching and Clock-Feedthrough Errors. | Alberto Yufera, Adoracin Rueda, Jos L. Huertas |
| 1994 | VTS | A new strategy for testing analog filters. | Diego Vzquez, Adoracin Rueda, Jos Luis Huertas |
| 1992 | VTS | On-line testing of switched-capacitor filters. | Jos Luis Huertas, Diego Vzquez, Adoracin Rueda |