| 2025 | ITC | Chiplet Interconnect Test and Repair. | Po-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen |
| 2024 | ETS | Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. | Cheng-Wen Wu, Shi-Yu Huang |
| 2023 | ASPDAC | A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks. | Pai-Yu Tan, Cheng-Wen Wu |
| 2023 | VTS | Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. | Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen |
| 2022 | ITC | Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. | Ya-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao |
| 2022 | ITC | Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. | Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu |
| 2021 | DATE | An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. | Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu |
| 2020 | DAC | A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. | Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu |
| 2020 | ETS | Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. | Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen |
| 2020 | ITC | A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. | Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang |
| 2019 | ITC | Asian Test Symposium - Past, Present and Future -. | Michiko Inoue, Xiaowei Li, Cheng-Wen Wu |
| 2018 | ACSSC | A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning. | Ying-Cih Kao, Cheng-Wen Wu |
| 2018 | ETS | Covering hard-to-detect defects by thermal quorum sensing. | Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen |
| 2018 | ITC | Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. | Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu |
| 2017 | ITC | Highly reliable and low-cost symbiotic IOT devices and systems. | Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu |
| 2016 | DAC | Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. | Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2016 | ETS | A fast sweep-line-based failure pattern extractor for memory diagnosis. | Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu |
| 2016 | ETS | Is IoT coming to the rescue of semiconductor? | Cheng-Wen Wu |
| 2014 | ITC | Redundancy architectures for channel-based 3D DRAM yield improvement. | Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2013 | ASPDAC | Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. | Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2013 | DATE | An enhanced double-TSV scheme for defect tolerance in 3D-IC. | Hsiu-Chuan Shih, Cheng-Wen Wu |
| 2013 | ISLPED | Holistic approach to low-power system design. | Cheng-Wen Wu |
| 2013 | VTS | 3D-IC interconnect test, diagnosis, and repair. | Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin |
| 2013 | VTS | Special session 4C: Hot topic 3D-IC design and test. | Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai |
| 2013 | VTS | A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. | Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2012 | ASPDAC | On test and repair of 3D random access memory. | Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li |
| 2012 | ITC | A memory yield improvement scheme combining built-in self-repair and error correction codes. | Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang |
| 2012 | ITC | A built-in self-test scheme for 3D RAMs. | Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2012 | VTS | Cost modeling and analysis for interposer-based three-dimensional IC. | Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu |
| 2012 | VTS | A Memory Failure Pattern Analyzer for memory diagnosis and repair. | Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu |
| 2011 | ASPDAC | A self-testing and calibration method for embedded successive approximation register ADC. | Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu |
| 2011 | DAC | A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. | Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang |
| 2011 | ETS | DfT Architecture for 3D-SICs with Multiple Towers. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | ITC | Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | VTS | A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. | Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2011 | VTS | Training-based forming process for RRAM yield improvement. | Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu |
| 2011 | VTS | Special session: Hot topic design and test of 3D and emerging memories. | Cheng-Wen Wu |
| 2010 | ASPDAC | Is 3D integration an opportunity or just a hype? | Jin-Fu Li, Cheng-Wen Wu |
| 2010 | DAC | An error tolerance scheme for 3D CMOS imagers. | Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu |
| 2010 | DAC | Fast identification of operating current for toggle MRAM by spiral search. | Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu |
| 2010 | DATE | An adaptive code rate EDAC scheme for random access memory. | Ching-Yi Chen, Cheng-Wen Wu |
| 2010 | ETS | A low-cost and scalable test architecture for multi-core chips. | Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li |
| 2010 | VTS | On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. | Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai |
| 2009 | VTS | An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. | Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu |
| 2007 | ITC | Diagnosis for MRAM write disturbance fault. | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao |
| 2007 | VTS | SDRAM Delay Fault Modeling and Performance Testing. | Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2006 | DAC | A network security processor design based on an integrated SOC design and test platform. | Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang |
| 2006 | ITC | An Enhanced EDAC Methodology for Low Power PSRAM. | Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin |
| 2006 | ITC | Testing MRAM for Write Disturbance Fault. | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao |
| 2006 | VTS | A Built-In Self-Repair Scheme for NOR-Type Flash Memory. | Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu |
| 2006 | VTS | Session Abstract. | Cheng-Wen Wu |
| 2005 | ASPDAC | A configurable AES processor for enhanced security. | Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | ASPDAC | Design and test of a scalable security processor. | Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | DATE | SOC Testing Methodology and Practice. | Cheng-Wen Wu |
| 2005 | VTS | A BIST Scheme for FPGA Interconnect Delay Faults. | Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | VTS | Flash Memory Built-In Self-Diagnosis with Test Mode Control. | Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin |
| 2004 | ASPDAC | SRAM delay fault modeling and test algorithm development. | Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu |
| 2004 | ASPDAC | An HMAC processor with integrated SHA-1 and MD5 algorithms. | Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu |
| 2004 | ITC | MRAM Defect Analysis and Fault Modeli. | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu |
| 2003 | ASPDAC | A highly efficient AES cipher chip. | Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | ASPDAC | Design of a scalable RSA and ECC crypto-processor. | Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | ICCAD | FAME: A Fault-Pattern Based Memory Failure Analysis Framework. | Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu |
| 2003 | ISCAS | Combinational circuit fault diagnosis using logic emulation. | Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang |
| 2003 | ITC | A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
| 2003 | ITC | Fault Pattern Oriented Defect Diagnosis for Memories. | Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang |
| 2003 | VTS | Test and Diagnosis of Word-Oriented Multiport Memories. | Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2002 | DATE | A Hierarchical Test Scheme for System-On-Chip Designs. | Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin |
| 2002 | IOLTS | A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
| 2002 | ITC | Diagonal Test and Diagnostic Schemes for Flash Memorie. | Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu |
| 2002 | VTS | RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. | Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu |
| 2002 | VTS | Testing and Diagnosing Embedded Content Addressable Memories. | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
| 2001 | ASPDAC | Processor-programmable memory BIST for bus-connected embedded memories. | Ching-Hong Tsai, Cheng-Wen Wu |
| 2001 | ASPDAC | RSA cryptosystem design based on the Chinese remainder theorem. | Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu |
| 2001 | DAC | Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu |
| 2001 | DATE | Memory fault diagnosis by syndrome compression. | Jin-Fu Li, Cheng-Wen Wu |
| 2001 | ITC | March-based RAM diagnosis algorithms for stuck-at and coupling faults. | Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2001 | VTS | Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. | Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu |
| 2000 | ASPDAC | Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. | Jin-Hua Hong, Cheng-Wen Wu |
| 2000 | ASPDAC | A programmable built-in self-test core for embedded memories. | Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu |
| 2000 | DATE | Cost and Benefit Models for Logic and Memory BIST. | Juin-Ming Lu, Cheng-Wen Wu |
| 2000 | ICCAD | Error Catch and Analysis for Semiconductor Memories Using March Tests. | Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu |
| 2000 | ISCAS | Built-in self-test and fault diagnosis for lookup table FPGAs. | Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu |
| 2000 | VTS | Simulation-Based Test Algorithm Generation for Random Access Memories. | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu |
| 1999 | ASPDAC | Testing Interconnects of Dynamic Reconfigurable FPGAs. | Chi-Feng Wu, Cheng-Wen Wu |
| 1999 | ISCAS | A novel approach to testing LUT-based FPGAs. | Shyue-Kung Lu, Cheng-Wen Wu |
| 1997 | DATE | High-speed C-testable systolic array design for Galois-field inversion. | Chih-Tsun Huang, Cheng-Wen Wu |
| 1994 | ISCAS | General Modular Multiplication by Block Multiplication and Table Lookup. | Cheng-Wen Wu, Yung-Fa Chou |
| 1991 | ICCD | Designing Self-Testable Cellular Arrays. | Cheng-Wen Wu, Shyue-Kung Lu |
| 1987 | ICASSP | Computer-aided design of VLSI second-order sections. | Cheng-Wen Wu, Peter R. Cappello |