| 2002 | DAC | Low-cost sequential ATPG with clock-control DFT. | Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick |
| 2002 | GECCO | Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm. | Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick |
| 2002 | ICTAI | A Genetic Testing Framework for Digital Integrated Circuits. | Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick |
| 2001 | CEC | A genetic approach to automatic bias generation for biased random instruction generation. | Mrinal Bose, Jongshin Shin, Elizabeth M. Rudnick, Todd Dukes, Magdy Abadir |
| 2001 | IOLTS | Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. | Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir |
| 2001 | ITC | At-speed logic BIST using a frozen clock testing strategy. | Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici |
| 2001 | VTS | Automatic Generation of Diagnostic March Tests. | Dirk Niggemeyer, Elizabeth M. Rudnick |
| 2000 | DATE | Diagnostic Testing of Embedded Memories Using BIST. | Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick |
| 2000 | ETS | Combining symbolic and genetic techniques for efficient sequential circuit test generation. | Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick |
| 2000 | ITC | Diagnostic test generation for sequential circuits. | Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick |
| 1999 | DATE | FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. | Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici |
| 1999 | DATE | A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. | Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick |
| 1999 | VLSID | A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. | Jue Wu, Elizabeth M. Rudnick |
| 1998 | DATE | Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. | Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda |
| 1998 | ICCD | Enhancing topological ATPG with high-level information and symbolic techniques. | Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti |
| 1998 | VLSID | Partial Scan Selection Based on Dynamic Reachability and Observability Information. | Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | DATE | Sequential circuit test generation using dynamic state traversal. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | ICCAD | Effects of delay models on peak power estimation of VLSI sequential circuits. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | ISLPED | K2: an estimator for peak sustainable power of VLSI circuits. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | ITC | Putting the Squeeze on Test Sequences. | Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | PADS | Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. | Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | VLSID | Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. | Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | VLSID | Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. | Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee |
| 1997 | VLSID | Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. | Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | VTS | Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | VTS | SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. | Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee |
| 1997 | VTS | Static logic implication with application to redundancy identification. | Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | DATE | Alternating Strategies for Sequential Circuit ATPG. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | ICCAD | Enhancing high-level control-flow for improved testability. | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | ICCAD | Simulation-based techniques for dynamic test sequence compaction. | Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | ITC | On Potential Fault Detection in Sequential Circuits. | Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz |
| 1996 | VTS | Automatic test generation using genetically-engineered distinguishing sequences. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | VTS | Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. | Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel |
| 1995 | DAC | Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. | Elizabeth M. Rudnick, Janak H. Patel |
| 1995 | DAC | Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. | Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel |
| 1995 | VLSID | A genetic approach to test application time reduction for full scan and partial scan circuits. | Elizabeth M. Rudnick, Janak H. Patel |
| 1994 | DAC | Sequential Circuit Test Generation in a Genetic Algorithm Framework. | Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann |
| 1993 | DAC | Non-Scan Design-for-Testability Techniques for Sequential Circuits. | Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel |
| 1992 | ITC | Diagnostic Fault Simulation of Sequential Circuits. | Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel |
| 1992 | VTS | Probe point insertion for at-speed test. | Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel |
| 1991 | ICCAD | Methods for Reducing Events in Sequential Circuit Fault Simulation. | Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel |