| 2021 | DAC | Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. | Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi |
| 2021 | IOLTS | CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models. | Kensuke Murakami, Mahfuzul Islam, Hidetoshi Onodera |
| 2020 | ICCAD | MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. | Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera |
| 2019 | ASPDAC | BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. | Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi |
| 2019 | DAC | NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. | Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera |
| 2018 | ICCAD | PVT | A. K. M. Mahfuzul Islam, Hidetoshi Onodera |
| 2018 | IOLTS | Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. | Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera |
| 2016 | ASPDAC | A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. | Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
| 2016 | ASPDAC | On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations. | Islam A. K. M. Mahfuzul, Hidetoshi Onodera |
| 2016 | FPL | A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. | Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto |
| 2015 | ASPDAC | Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. | Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera |
| 2015 | ASPDAC | Microarchitectural-level statistical timing models for near-threshold circuit design. | Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
| 2014 | ISCAS | A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. | Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai |
| 2013 | ASPDAC | A 25-Gb/s LD driver with area-effective inductor in a 0.18-m CMOS. | Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera |
| 2013 | ASPDAC | Dependable VLSI Platform using Robust Fabrics. | Hidetoshi Onodera |
| 2013 | IOLTS | Perturbation-immune radiation-hardened PLL with a switchable DMR structure. | SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera |
| 2012 | ASPDAC | A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18m CMOS. | Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera |
| 2012 | ICCD | A flexible structure of standard cell and its optimization method for near-threshold voltage operation. | Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera |
| 2011 | ASPDAC | A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. | Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2009 | ASPDAC | Dependable VLSI: device, design and architecture: how should they cooperate? | Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe |
| 2008 | ASPDAC | Statistical gate delay model for Multiple Input Switching. | Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera |
| 2008 | ASPDAC | Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. | Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2008 | FPGA | Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2008 | FPL | A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. | Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera |
| 2008 | FPL | Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2007 | ASPDAC | A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. | Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera |
| 2007 | ASPDAC | A 90nm 816 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. | Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2006 | ASPDAC | Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. | Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2006 | ASPDAC | Interconnect RL extraction at a single representative frequency. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2006 | FPL | A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. | Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera |
| 2005 | ASPDAC | Timing analysis considering temporal supply voltage fluctuation. | Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera |
| 2005 | ASPDAC | A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. | Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera |
| 2005 | ASPDAC | Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. | Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera |
| 2005 | ASPDAC | Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18m CMOS process. | Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera |
| 2005 | ASPDAC | Return path selection for loop RL extraction. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2004 | ASPDAC | A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. | Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera |
| 2004 | ASPDAC | Representative frequency for interconnect R(f)L(f)C extraction. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2004 | ASPDAC | An SoC architecture and its design methodology using unifunctional heterogeneous processor array. | Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2004 | ICCAD | Timing analysis considering spatial power/ground level variation. | Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera |
| 2004 | ISCAS | Modelling and optimization of on-chip spiral inductor in S-parameter domain. | Ken-ichi Okada, Hiroaki Hoshino, Hidetoshi Onodera |
| 2004 | ISCAS | RTL/ISS co-modeling methodology for embedded processor using SystemC. | Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2003 | ASPDAC | Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. | Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera |
| 2003 | ASPDAC | A statistical gate delay model for intra-chip and inter-chip variabilities. | Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera |
| 2003 | ICCAD | Equivalent Waveform Propagation for Static Timing Analysis. | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
| 2003 | ICCAD | A Statistical Gate-Delay Model Considering Intra-Gate Variability. | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
| 2003 | ISCAS | Statistical modeling of gate-delay variation with consideration of intra-gate variability. | Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera |
| 2001 | ASPDAC | Post-layout transistor sizing for power reduction in cell-based design. | Masanori Hashimoto, Hidetoshi Onodera |
| 2001 | ASPDAC | A vector-pipeline DSP for low-rate videophones. | Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera |
| 2001 | ASPDAC | Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. | Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori |
| 2001 | ASPDAC | A dynamically phase adjusting PLL with a variable delay. | Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera |
| 2001 | ICCD | Crosstalk Noise Estimation for Generic RC Trees. | Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera |
| 2001 | ISCAS | ST: PERL package for simulation and test environment. | Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2000 | ASPDAC | A method for linking process-level variability to system performances. | Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru |
| 2000 | ISCAS | Statistical delay calculation with vector synthesis model. | Tomohiro Fujita, Hidetoshi Onodera |
| 2000 | ISCAS | Statistical modeling of device characteristics with systematic fluctuation. | Kenichi Okada, Hidetoshi Onodera |
| 1999 | DAC | A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
| 1998 | ICCAD | Proposal of a timing model for CMOS logic gates driving a CRC load. | Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru |
| 1998 | ISLPED | A power optimization method considering glitch reduction by gate sizing. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | ASPDAC | A functional memory type parallel processor for vector quantization. | Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru |
| 1997 | ASPDAC | A current mode cyclic A/D converter with a 0.8 μm CMOS process. | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | ASPDAC | A model-adaptable MOSFET parameter extraction system. | Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | ICCAD | An iterative gate sizing approach with accurate delay evaluation. | Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
| 1993 | ICCAD | Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. | Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru |
| 1991 | DAC | Branch-and-Bound Placement for Building Block Layout. | Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru |
| 1989 | ICCAD | An efficient algorithm for layout compaction problem with symmetry constraints. | R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu |