| 2020 | DATE | Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. | Paul Detterer, Cumhur Erdin, Jos Huisken, Hailong Jiao, Majid Nabi, Twan Basten, Jos Pineda de Gyvez |
| 2020 | DATE | Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN. | Emad A. Ibrahim, Marc Geilen, Jos Huisken, Min Li, Jos Pineda de Gyvez |
| 2019 | DATE | Chip Health Tracking Using Dynamic In-Situ Delay Monitoring. | Hadi Ahmadi Balef, Kees Goossens, Jos Pineda de Gyvez |
| 2019 | DATE | Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. | Paul Detterer, Cumhur Erdin, Majid Nabi, Jos Pineda de Gyvez, Twan Basten, Hailong Jiao |
| 2019 | DSD | Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. | Emad A. Ibrahim, Jos Huisken, Hamed Fatemi, Jos Pineda de Gyvez |
| 2018 | ISCAS | Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. | Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, Jos Pineda de Gyvez |
| 2017 | ASPDAC | Floorplan and placement methodology for improved energy reduction in stacked power-domain design. | Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, Jos Pineda de Gyvez |
| 2017 | DATE | A scan-chain based state retention methodology for IoT processors operating on intermittent energy. | Pascal Alexander Hager, Hamed Fatemi, Jos Pineda de Gyvez, Luca Benini |
| 2016 | DAC | Lower power by voltage stacking: a fine-grained system design approach. | Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, Jos Pineda de Gyvez |
| 2016 | ICCAD | Circuit valorization in the IC design ecosystem. | Jos Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt |
| 2015 | DATE | Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. | Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, Jos Pineda de Gyvez |
| 2014 | DATE | Standard cell library tuning for variability tolerant designs. | Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, Jos Pineda de Gyvez |
| 2014 | DATE | Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. | Yu Pu, Juan Diego Echeverri, Maurice Meijer, Jos Pineda de Gyvez |
| 2012 | DAC | Standard cell sizing for subthreshold operation. | Bo Liu, Maryam Ashouei, Jos Huisken, Jos Pineda de Gyvez |
| 2012 | DATE | Sliding-Mode Control to Compensate PVT Variations in dual core systems. | Hamid Reza Pourshaghaghi, Hamed Fatemi, Jos Pineda de Gyvez |
| 2011 | DSD | Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. | Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, Jos Pineda de Gyvez |
| 2011 | ISLPED | A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. | Amir Zjajo, Jos Pineda de Gyvez |
| 2010 | ISCAS | A forward body bias generator for digital CMOS circuits with supply voltage scaling. | Maurice Meijer, Jos Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt |
| 2008 | DATE | Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. | Amir Zjajo, Jos Pineda de Gyvez |
| 2008 | DDECS | Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. | Amir Zjajo, Shaji Krishnan, Jos Pineda de Gyvez |
| 2007 | DATE | Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. | Amir Zjajo, Manuel J. Barragan Asian, Jos Pineda de Gyvez |
| 2006 | ETS | Testing and Diagnosis of Power Switches in SOCs. | Sandeep Kumar Goel, Maurice Meijer, Jos Pineda de Gyvez |
| 2005 | ETS | Evaluation of signature-based testing of RF/analog circuits. | Amir Zjajo, Jos Pineda de Gyvez |
| 2005 | ISCAS | Limits to performance spread tuning using adaptive voltage and body biasing. | Maurice Meijer, Francesco Pessolano, Jos Pineda de Gyvez |
| 2005 | ISCAS | Glitch-free discretely programmable clock generation on chip. | Maurice Meijer, Francesco Pessolano, Jos Pineda de Gyvez |
| 2005 | ISLPED | On-chip digital power supply control for system-on-chip applications. | Maurice Meijer, Jos Pineda de Gyvez, Ralph Otten |
| 2005 | ITC | Word line pulsing technique for stability fault detection in SRAM cells. | Andrei Pavlov, Mohamed Azimane, Jos Pineda de Gyvez, Manoj Sachdev |
| 2005 | ITC | Functional vs. multi-VDD testing of RF circuits. | Estella Silva, Jos Pineda de Gyvez, Guido Gronthoud |
| 2005 | ITC | Power-scan chain: design for analog testability. | Amir Zjajo, Henk Jan Bergveld, Rodger Schuttert, Jos Pineda de Gyvez |
| 2004 | DATE | Power Supply Noise Monitor for Signal Integrity Faults. | Josep Rius Vzquez, Jos Pineda de Gyvez |
| 2004 | FPGA | Low energy FPGA interconnect design. | Rohini Krishnan, Jos Pineda de Gyvez, Martijn T. Bennebroek |
| 2004 | ISLPED | Technology exploration for adaptive power and frequency scaling in 90nm CMOS. | Maurice Meijer, Francesco Pessolano, Jos Pineda de Gyvez |
| 2004 | ITC | Power Supply Ramping for Quasi-static Testing of PLLs. | Jos Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller |
| 2004 | ITC | AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. | Andrei Pavlov, Manoj Sachdev, Jos Pineda de Gyvez |
| 2004 | VLSID | Low Energy Switch Block For FPGAs. | Rohini Krishnan, Jos Pineda de Gyvez |
| 2004 | VTS | Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. | Josep Rius Vzquez, Jos Pineda de Gyvez |
| 2003 | ETS | Process-variability aware delay fault testing of ΔV | Daniel Arum-Delgado, Rosa Rodrguez-Montas, Jos Pineda de Gyvez, Guido Gronthoud |
| 2003 | FPL | Encoded-Low Swing Technique for Ultra Low Power Interconnect. | Rohini Krishnan, Jos Pineda de Gyvez, Harry J. M. Veendrick |
| 2003 | ITC | VDD Ramp Testing for RF Circuits. | Jos Pineda de Gyvez, Guido Gronthoud, Rashid Amine |
| 2003 | VTS | Threshold Voltage Mismatch (DeltaVT) Fault Modeling. | Jos Pineda de Gyvez, Rosa Rodrguez-Montas |
| 2001 | VTS | Average Leakage Current Estimation of CMOS Logic Circuits. | Jos Pineda de Gyvez, Eric van de Wetering |
| 1999 | ISCAS | Chaotic generation of PN sequences: a VLSI implementation. | A. Dornbusch, Jos Pineda de Gyvez |
| 1999 | ISCAS | CMOS cryptosystem using a Lorenz chaotic oscillator. | Octavio A. Gonzlez, Gunhee Han, Jos Pineda de Gyvez, Edgar Snchez-Sinencio |
| 1997 | ICEC | DNA computing based on chaos. | Gabriele Manganaro, Jos Pineda de Gyvez |
| 1995 | ISCAS | A Universal Interface Between PC and Neural Networks Hardware. | Apollo Q. Fong, Ajay Kanji, Edgar Snchez-Sinencio, Jos Pineda de Gyvez |
| 1995 | ISCAS | Time Domain Analog Wavelet Transform in Real-Time. | Oscar Moreira-Tamayo, Jos Pineda de Gyvez |
| 1994 | ISCAS | Single-Layer CNN Simulator. | Chi-Chien Lee, Jos Pineda de Gyvez |
| 1994 | ISCAS | Time-Mulitplexing CNN Simulator. | Chi-Chien Lee, Jos Pineda de Gyvez |
| 1994 | ISCAS | Behavioral Testing of Cellular Neural Networks. | John Willis, Jos Pineda de Gyvez |
| 1994 | VTS | A power supply ramping and current measurement based technique for analog fault diagnosis. | Shyam S. Somayajula, Edgar Snchez-Sinencio, Jos Pineda de Gyvez |
| 1989 | ICCAD | A layout defect-sensitivity extractor. | Jos Pineda de Gyvez, Jochen A. G. Jess |