| 2019 | MVA | Exploring Better Food Detection via Transfer Learning. | Jianing Sun, Katarzyna Radecka, Zeljko Zilic |
| 2014 | BIBE | Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. | Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic |
| 2013 | ETS | A minimum MSE sensor fusion algorithm with tolerance to multiple faults. | Omid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka |
| 2013 | BSN | An efficient fault-tolerant sensor fusion algorithm for accelerometers. | Omid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica |
| 2012 | ASPDAC | Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. | Omid Sarbishei, Katarzyna Radecka |
| 2012 | ICCD | MSE minimization and fault-tolerant data fusion for multi-sensor systems. | Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic |
| 2012 | ISCAS | Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). | Omid Sarbishei, Katarzyna Radecka |
| 2011 | ARITH | On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. | Omid Sarbishei, Katarzyna Radecka |
| 2011 | ASPDAC | An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. | Yu Pang, Katarzyna Radecka, Zeljko Zilic |
| 2011 | ICCD | Positive Davio-based synthesis algorithm for reversible logic. | Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka |
| 2011 | ICCD | A study on relating redundancy removal in classical circuits to reversible mapping. | Sayeeda Sultana, Katarzyna Radecka, Yu Pang |
| 2011 | ISCAS | A novel method of synthesizing reversible logic. | Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka |
| 2011 | ISCAS | An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking. | Yu Pang, Katarzyna Radecka |
| 2011 | ISCAS | Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. | Omid Sarbishei, Katarzyna Radecka |
| 2010 | ICCAD | Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. | Omid Sarbishei, Katarzyna Radecka |
| 2008 | DAC | Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. | Yu Pang, Katarzyna Radecka |
| 2007 | DATE | Reversible circuit technology mapping from non-reversible specifications. | Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur |
| 2006 | VTS | Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. | Rong Zhang, Zeljko Zilic, Katarzyna Radecka |
| 2004 | ICCD | FPGA Emulation of Quantum Circuits. | Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka |
| 2004 | ITC | Architectures of Increased Availability Wireless Sensor Network Nodes. | Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka |
| 2002 | ICCAD | Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. | Katarzyna Radecka, Zeljko Zilic |
| 2002 | VLSID | Identifying Redundant Wire Replacements for Synthesis and Verification. | Katarzyna Radecka, Zeljko Zilic |
| 2001 | ICCD | Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. | Katarzyna Radecka, Zeljko Zilic |
| 2001 | ITC | : Identifying redundant gate replacements in verification by error modeling. | Zeljko Zilic, Katarzyna Radecka |
| 2000 | VTS | Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. | Katarzyna Radecka, Zeljko Zilic |
| 1999 | ISSAC | On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. | Zeljko Zilic, Katarzyna Radecka |