Luigi Dilillo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
60
Venues
8
Active years
2004–2026
Best venue rank
A*
Where they publish
Papers
60 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ETS | STA-Based Single Event Transient Propagation in Advanced Technology Nodes. | Nikolaos Chatzivangelis, Marios Karagiannis, Christos Georgakidis, Nikolaos Sketopoulos, Marko S. Andjelkovic, Luigi Dilillo, Christos P. Sotiriou |
| 2026 | VTS | Soft Error Reliability Analysis & Hardening of NVDLA MAC Units. | Nikolaos Chatzivangelis, Nikolaos Betsos, Georgios Ioannis Paliaroutis, Nikolaos Zazatis, Pelopidas Tsoumanis, Frederic Wrobel, Marko S. Andjelkovic, Christos P. Sotiriou, Luigi Dilillo |
| 2026 | VTS | Reliability Evaluation of Vector-Accelerated Neural Network Inference on a Fault-Tolerant RISC-V SoC for Space Applications. | Carolina Imianosky, Douglas A. dos Santos, Wesley Grignani, Luigi Dilillo |
| 2025 | DATE | Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT). | Marko S. Andjelkovic, Fabian Vargas, Milos Krstic, Luigi Dilillo, Alain Michez, Frederic Wrobel, Davide Bertozzi, Mikel Lujn, Christos Georgakidis, Nikolaos Chatzivangelis, Katerina Tsilingiri, Nikolaos Zazatis, Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Christos P. Sotiriou |
| 2022 | ETS | Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. | Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo |
| 2021 | DDECS | A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. | Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Snchez, Luigi Dilillo |
| 2017 | ETS | Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps. | Marcelino Seif, Emna Farjallah, Franck Badets, Emna Chabchoub, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Luigi Dilillo, Valentin Gherman |
| 2017 | ITC | Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics. | Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo |
| 2015 | DATE | Exploring the impact of functional test programs re-used for power-aware testing. | Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda |
| 2015 | DDECS | Design-for-Diagnosis Architecture for Power Switches. | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot |
| 2015 | ETS | An effective hybrid fault-tolerant architecture for pipelined cores. | Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard |
| 2014 | ASPDAC | Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. | Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel |
| 2014 | DDECS | Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. | Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2014 | DDECS | An intra-cell defect grading tool. | Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi |
| 2014 | DDECS | Timing-aware ATPG for critical paths with multiple TSVs. | Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel |
| 2014 | DDECS | Test and diagnosis of power switches. | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot |
| 2014 | DDECS | Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. | Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri |
| 2014 | ETS | iBoX - Jitter based Power Supply Noise sensor. | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot |
| 2014 | VTS | TSV aware timing analysis and diagnosis in paths with multiple TSVs. | Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel |
| 2013 | DATE | Test solution for data retention faults in low-power SRAMs. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine |
| 2013 | ETS | Computing detection probability of delay defects in signal line tsvs. | Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville |
| 2013 | ETS | Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. | Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine |
| 2013 | IOLTS | SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. | Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frdric Saign |
| 2013 | ITC | On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine |
| 2013 | VTS | A built-in scheme for testing and repairing voltage regulators of low-power srams. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine |
| 2012 | DATE | Impact of resistive-open defects on the heat current of TAS-MRAM architectures. | Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jrmy Alvarez-Herault, Ken Mackay |
| 2012 | ETS | Coupling-based resistive-open defects in TAS-MRAM architectures. | Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jrmy Alvarez-Herault, Ken Mackay |
| 2012 | ETS | Through-Silicon-Via resistive-open defect analysis. | Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel |
| 2012 | ETS | Defect analysis in power mode control logic of low-power SRAMs. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine |
| 2012 | IOLTS | Evaluation of test algorithms stress effect on SRAMs under neutron radiation. | Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frdric Saign |
| 2012 | ITC | Low-power SRAMs power mode control logic: Failure analysis and test solutions. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine |
| 2012 | VTS | Advanced test methods for SRAMs. | Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2012 | VTS | A pseudo-dynamic comparator for error detection in fault tolerant architectures. | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich |
| 2011 | DDECS | On using a SPICE-like TSTAC™ eFlash model for design and test. | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard, Gilles Festes, Laurent Vachez |
| 2011 | DDECS | A study of path delay variations in the presence of uncorrelated power and ground supply noise. | Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2011 | DDECS | Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2011 | ETS | A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Snchez, Mauricio de Carvalho, Matteo Sonza Reorda |
| 2011 | ITC | On using address scrambling to implement defect tolerance in SRAMs. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | DAC | A statistical simulation method for reliability analysis of SRAM core-cells. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | DDECS | Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen |
| 2010 | ETS | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | ETS | Setting test conditions for improving SRAM reliability. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | ETS | A two-layer SPICE model of the ATMEL TSTAC | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard, Gilles Festes, Laurent Vachez |
| 2010 | IOLTS | Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts. | Paolo Rech, Michelangelo Grosso, Fabio Melchiori, Domenico Loparco, Davide Appello, Luigi Dilillo, Alessandro Paccagnella, Matteo Sonza Reorda |
| 2010 | ITC | A roaming memory test bench for detecting particle induced SEUs. | Jean-Marc Gallire, Paolo Rech, Patrick Girard, Luigi Dilillo |
| 2010 | ITC | Parity prediction synthesis for nano-electronic gate designs. | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
| 2010 | ITC | Is test power reduction through X-filling good enough? | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed |
| 2010 | VTS | Detecting NBTI induced failures in SRAM core-cells. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2009 | DATE | A new design-for-test technique for SRAM core-cell stability faults. | Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
| 2009 | DDECS | Comprehensive bridging fault diagnosis based on the SLAT paradigm. | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute |
| 2009 | ITC | NAND flash testing: A preliminary study on actual defects. | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard |
| 2008 | ITC | A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. | Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2007 | DDECS | March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. | Luigi Dilillo, Bashir M. Al-Hashimi |
| 2006 | DATE | Minimizing test power in SRAM through reduction of pre-charge activity. | Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard |
| 2006 | DDECS | March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2005 | DAC | Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 m and 90 nm technologies. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2005 | ETS | Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
| 2005 | VTS | Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
| 2004 | ETS | Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
| 2004 | VTS | March iC-: An Improved Version of March C- for ADOFs Detection. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri |