| 2025 | DATE | Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. | Filip Masar, Vojtech Mrazek, Luks Sekanina |
| 2025 | DDECS | Inference Energy Analysis in Context of Hardware-Aware NAS. | Michal Pinos, Jan Klhufek, Vojtech Mrazek, Luks Sekanina |
| 2025 | EUROGP | Multi-objective Evolutionary Design of Explainable EEG Classifier. | Martin Hurta, Anna Ovesna, Vojtech Mrazek, Luks Sekanina |
| 2024 | DATE | Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2024 | DDECS | Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. | Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2024 | ICCD | Tutorial: Evolutionary Design Methods in Electronic Design Automation. | Luks Sekanina |
| 2024 | IJCNN | ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. | Michal Pinos, Luks Sekanina, Vojtech Mrazek |
| 2023 | DATE | ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. | Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Luks Sekanina |
| 2023 | DDECS | MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. | Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Luks Sekanina |
| 2023 | DDECS | Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. | Michal Pinos, Vojtech Mrazek, Luks Sekanina |
| 2023 | EUROGP | GPAM: Genetic Programming with Associative Memory. | Tadeas Juza, Luks Sekanina |
| 2023 | GECCO | Evolution of Editing Scripts From Examples. | Marek Sedlacek, Luks Sekanina |
| 2023 | ICCAD | Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. | Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2022 | EUROGP | Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. | Martin Hurta, Michaela Drahosova, Luks Sekanina, Stephen L. Smith, Jane E. Alty |
| 2022 | SMC | Evolutionary Approximation in Non-Local Means Image Filters. | Matej Valek, Luks Sekanina |
| 2021 | EUROGP | Evolutionary Neural Architecture Search Supporting Approximate Multipliers. | Michal Pinos, Vojtech Mrazek, Luks Sekanina |
| 2020 | CEC | Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. | David Grochol, Luks Sekanina |
| 2020 | CEC | Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. | Jakub Husa, Luks Sekanina |
| 2020 | DAC | ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. | Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2020 | DATE | TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. | Filip Vaverka, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2020 | ETS | Design, Verification, Test and In-Field Implications of Approximate Computing Systems. | Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Snchez, Alessandro Savino, Luks Sekanina, Marcello Traiola, Zdenek Vascek, Arnaud Virazel |
| 2019 | DAC | autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. | Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2019 | DATE | TypeCNN: CNN Development Framework With Flexible Data Types. | Petr Rek, Luks Sekanina |
| 2019 | DATE | Automated Circuit Approximation Method Driven by Data Distribution. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2019 | EUROGP | Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. | Ondrej Koncal, Luks Sekanina |
| 2019 | ICCAD | ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. | Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique |
| 2019 | ITC | International Symposium on Design and Diagnostics of Electronic Circuits and Systems. | Zoran Stamenkovic, Alberto Bosio, Gyrgy Cserey, Ondrej Novk, Witold A. Pleskacz, Luks Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjakov |
| 2018 | CAV | ADAC: Automated Design of Approximate Circuits. | Milan Ceska, Jir Matys, Vojtech Mrazek, Luks Sekanina, Zdenek Vascek, Toms Vojnar |
| 2018 | EUROGP | Multi-objective Evolution of Ultra-Fast General-Purpose Hash Functions. | David Grochol, Luks Sekanina |
| 2018 | GECCO | Evolving boolean functions for fast and efficient randomness testing. | Vojtech Mrazek, Marek Ss, Zdenek Vascek, Luks Sekanina, Vashek Matyas |
| 2018 | VTS | Special session: How approximate computing impacts verification, test and reliability. | Luks Sekanina, Zdenek Vascek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo |
| 2017 | CEC | Multi-objective evolution of hash functions for high speed networks. | David Grochol, Luks Sekanina |
| 2017 | DATE | EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. | Vojtech Mrazek, Radek Hrbacek, Zdenek Vascek, Luks Sekanina |
| 2017 | DATE | Towards low power approximate DCT architecture for HEVC standard. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2017 | EUROGP | On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. | Milos Minarik, Luks Sekanina |
| 2017 | ICCAD | Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. | Milan Ceska, Jir Matys, Vojtech Mrazek, Luks Sekanina, Zdenek Vascek, Toms Vojnar |
| 2016 | DDECS | Introduction to approximate computing: Embedded tutorial. | Luks Sekanina |
| 2016 | EUROGP | Evolutionary Approximation of Edge Detection Circuits. | Petr Dvoracek, Luks Sekanina |
| 2016 | FPL | Search-based synthesis of approximate circuits implemented into FPGAs. | Zdenek Vascek, Luks Sekanina |
| 2016 | GECCO | Evolutionary Design of Fast High-quality Hash Functions for Network Applications. | David Grochol, Luks Sekanina |
| 2016 | GECCO | Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. | Luks Sekanina, Vlastimil Kapusta |
| 2016 | ICCAD | Design of power-efficient approximate multipliers for approximate artificial neural networks. | Vojtech Mrazek, Syed Shakib Sarwar, Luks Sekanina, Zdenek Vascek, Kaushik Roy |
| 2015 | EUROGP | Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. | Michaela Sikulov, Jiri Hulva, Luks Sekanina |
| 2015 | EUROGP | Circuit Approximation Using Single- and Multi-objective Cartesian GP. | Zdenek Vascek, Luks Sekanina |
| 2015 | GECCO | Evolutionary Approximation of Software for Embedded Systems: Median Function. | Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2015 | GECCO | Evolutionary Approximation of Complex Digital Circuits. | Zdenek Vascek, Luks Sekanina |
| 2014 | CEC | Cartesian genetic programming as local optimizer of logic networks. | Luks Sekanina, Ondrej Ptak, Zdenek Vascek |
| 2014 | DDECS | Evolutionary design of approximate multipliers under different error metrics. | Zdenek Vascek, Luks Sekanina |
| 2014 | EUROGP | Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. | Milos Minarik, Luks Sekanina |
| 2014 | GECCO | Towards highly optimized cartesian genetic programming: from sequential via SIMD and thread to massive parallel implementation. | Radek Hrbacek, Luks Sekanina |
| 2014 | PPSN | Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. | Jiri Petrlik, Otto Fuck, Luks Sekanina |
| 2013 | DDECS | Multiobjective evolution of approximate multiple constant multipliers. | Jiri Petrlik, Luks Sekanina |
| 2012 | CEC | Two-step evolution of polymorphic circuits for image multi-filtering. | Luks Sekanina, Vojtech Salajka, Zdenek Vascek |
| 2012 | CEC | On area minimization of complex combinational circuits using cartesian genetic programming. | Zdenek Vascek, Luks Sekanina |
| 2012 | DATE | Towards new applications of multi-function logic: Image multi-filtering. | Luks Sekanina, Vojtech Salajka |
| 2012 | DATE | A SAT-based fitness function for evolutionary optimization of polymorphic circuits. | Luks Sekanina, Zdenek Vascek |
| 2012 | EUROGP | Coevolution in Cartesian Genetic Programming. | Michaela Sikulov, Luks Sekanina |
| 2012 | EUROGP | Evolutionary Design of Message Efficient Secrecy Amplification Protocols. | Tobis Smolka, Petr Svenda, Luks Sekanina, Vashek Matys |
| 2012 | FPL | Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. | Rubn Salvador, Andrs Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Luks Sekanina |
| 2012 | PPSN | Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. | Michaela Sikulov, Luks Sekanina |
| 2011 | DATE | A global postsynthesis optimization method for combinational circuits. | Zdenek Vascek, Luks Sekanina |
| 2011 | DDECS | Behavior of CMOS polymorphic circuits in high temperature environment. | Richard Ruzicka, Vclav Simek, Luks Sekanina |
| 2011 | GECCO | Evolution of digital circuits. | Luks Sekanina |
| 2011 | KES | Evolution of Iterative Formulas Using Cartesian Genetic Programming. | Milos Minarik, Luks Sekanina |
| 2011 | UC | Increasing Fault-Tolerance in Cellular Automata-Based Systems. | Ludek Zaloudek, Luks Sekanina |
| 2010 | DATE | A method for design of impulse bursts noise filters optimized for FPGA implementations. | Zdenek Vascek, Luks Sekanina, Michal Bidlo |
| 2010 | DDECS | On logic synthesis of conventionally hard to synthesize circuits using genetic programming. | Petr Fiser, Jan Schmidt, Zdenek Vascek, Luks Sekanina |
| 2010 | DDECS | Evolutionary circuit design: Tutorial. | Luks Sekanina |
| 2010 | DDECS | On analysis of fabricated polymorphic circuits. | Vclav Simek, Richard Ruzicka, Luks Sekanina |
| 2010 | DSD | High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. | Rubn Salvador, Flix Moreno, Teresa Riesgo, Luks Sekanina |
| 2010 | GECCO | When does Cartesian genetic programming minimize the phenotype size implicitly? | Zbysek Gajda, Luks Sekanina |
| 2009 | CEC | Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming. | Zbysek Gajda, Luks Sekanina |
| 2009 | UC | Evolvable Hardware: From Applications to Implications for the Theory of Computation. | Luks Sekanina |
| 2008 | DDECS | Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. | Luks Starecek, Luks Sekanina, Zdenek Kotsek |
| 2008 | DDECS | Novel Hardware Implementation of Adaptive Median Filters. | Zdenek Vascek, Luks Sekanina |
| 2008 | EUROGP | Hardware Accelerators for Cartesian Genetic Programming. | Zdenek Vascek, Luks Sekanina |
| 2008 | IOLTS | Physical Demonstration of Polymorphic Self-Checking Circuits. | Richard Ruzicka, Luks Sekanina, Roman Prokop |
| 2008 | KES | Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. | Mircea Gh. Negoita, Luks Sekanina, Adrian Stoica |
| 2007 | DDECS | Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. | Luks Sekanina |
| 2007 | EUROGP | Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. | Karel Slan, Luks Sekanina |
| 2007 | FPL | An area-efficient alternative to adaptive median filtering in FPGAs. | Zdenek Vascek, Luks Sekanina |
| 2007 | GECCO | Reducing the number of transistors in digital circuits using gate-level evolutionary design. | Zbysek Gajda, Luks Sekanina |
| 2007 | GECCO | Evolvable hardware. | Luks Sekanina |
| 2006 | CEC | Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. | Luks Sekanina, Toms Martnek, Zbysek Gajda |
| 2006 | DDECS | FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. | Tomas Pecenka, Zdenek Kotsek, Luks Sekanina |
| 2006 | DDECS | Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. | Luks Sekanina, Luks Starecek, Zdenek Kotsek |
| 2006 | DSD | Testability Estimation Based on Controllability and Observability Parameters. | Tomas Pecenka, Josef Strnadel, Zdenek Kotsek, Luks Sekanina |
| 2005 | GECCO | Providing information from the environment for growing electronic circuits through polymorphic gates. | Michal Bidlo, Luks Sekanina |
| 2004 | PPSN | Recognizing Speed Limit Sign Numbers by Evolvable Hardware. | Jim Trresen, Jorgen W. Bakke, Luks Sekanina |
| 2004 | SOFSEM | Evolving Constructors for Infinitely Growing Sorting Networks and Medians. | Luks Sekanina |
| 2003 | EUROGP | From Implementations to a General Concept of Evolvable Machines. | Luks Sekanina |
| 2000 | FPL | Toward Uniform Approach to Design of Evolvable Hardware Based Systems. | Luks Sekanina, Azeddien M. Sllame |
| 2000 | IOLTS | Relation between Fault Tolerance and Reconfiguration in Cellular Systems. | Luks Sekanina, Vladimr Drbek |