| 2026 | VLSID | Universal Formal Verification Approach for Modular Reduction Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2024 | DATE | Combining Formal Verification and Testing for Debugging of Arithmetic Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2023 | DAC | Formal Verification of Restoring Dividers made Fast and Simple. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2023 | DSD | Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future. | Maciej J. Ciesielski |
| 2023 | ICCAD | Efficient Formal Verification and Debugging of Arithmetic Divider Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2022 | DDECS | Functional Verification of Arithmetic Circuits: Survey of Formal Methods. | Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari |
| 2020 | DATE | SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. | Atif Yasin, Tiankai Su, Sbastien Pillement, Maciej J. Ciesielski |
| 2019 | ASPDAC | Spectral approach to verifying non-linear arithmetic circuits. | Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski |
| 2018 | ISCAS | Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. | Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski |
| 2018 | LPAR | Rewriting Environment for Arithmetic Circuit Verification. | Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski |
| 2017 | ASPDAC | Efficient parallel verification of Galois field multipliers. | Cunxi Yu, Maciej J. Ciesielski |
| 2017 | DATE | Reverse engineering of irreducible polynomials in GF(2 | Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski |
| 2017 | ICCAD | Advanced datapath synthesis using graph isomorphism. | Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski |
| 2016 | DAC | DAG-aware logic synthesis of datapaths. | Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan |
| 2016 | ISCAS | Automatic word-level abstraction of datapath. | Cunxi Yu, Maciej J. Ciesielski |
| 2015 | DAC | Verification of gate-level arithmetic circuits by function extraction. | Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, Andr Rossi |
| 2015 | ISCAS | Verification of arithmetic datapath designs using word-level approach - A case study. | Cunxi Yu, Walter Brown, Maciej J. Ciesielski |
| 2014 | DATE | Fast STA prediction-based gate-level timing simulation. | Tariq B. Ahmad, Maciej J. Ciesielski |
| 2014 | DDECS | Fast time-parallel C-based event-driven RTL simulation. | Tariq Bashir Ahmad, Maciej J. Ciesielski |
| 2013 | DATE | FPGA latency optimization using system-level transformations and DFG restructuring. | Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier |
| 2011 | DATE | Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. | Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang |
| 2011 | DATE | A new distributed event-driven gate-level HDL simulation by accurate prediction. | Dusung Kim, Maciej J. Ciesielski, Seiyang Yang |
| 2011 | FMCAD | Algebraic approach to arithmetic design verification. | Mohamed Abdul Basith, Tariq B. Ahmad, Andr Rossi, Maciej J. Ciesielski |
| 2011 | VLSID | Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. | Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski |
| 2009 | DATE | Optimizing data flow graphs to minimize hardware implementation. | Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jrmie Guillot, Emmanuel Boutillon |
| 2008 | ASPDAC | A fast two-pass HDL simulation with on-demand dump. | Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang |
| 2008 | VLSID | Simulation Acceleration with HW Re-Compilation Avoidance. | Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang |
| 2007 | DATE | Data-flow transformations using Taylor expansion diagrams. | Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jrmie Guillot, Emmanuel Boutillon |
| 2006 | DATE | Efficient factorization of DSP transforms using taylor expansion diagrams. | Jrmie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar |
| 2005 | DSD | Yield-aware Floorplanning. | Zhaojun Wo, Israel Koren, Maciej J. Ciesielski |
| 2005 | ETS | Design validation of behavioral VHDL descriptions for arbitrary fault models. | Fei Xin, Maciej J. Ciesielski, Ian G. Harris |
| 2004 | DAC | A new state assignment technique for testing and low power. | Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski |
| 2003 | DATE | Fast Computation of Data Correlation Using BDDs. | Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski |
| 2002 | DATE | Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. | Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre |
| 2001 | DATE | LPSAT: a unified approach to RTL satisfiability. | Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski |
| 2000 | DAC | BDS: a BDD-based logic optimization system. | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
| 2000 | DATE | A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. | Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang |
| 2000 | DATE | Synthesis for Mixed CMOS/PTl Logic. | Congguang Yang, Maciej J. Ciesielski |
| 1999 | DATE | Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. | Priyank Kalla, Maciej J. Ciesielski |
| 1999 | ICCAD | Analytical approach to custom datapath design. | Serkan Askar, Maciej J. Ciesielski |
| 1999 | ICCD | BDD Decomposition for Efficient Logic Synthesis. | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
| 1998 | ICCAD | Reencoding for cycle-time minimization under fixed encoding length. | Balakrishnan Iyer, Maciej J. Ciesielski |
| 1998 | ITC | A comprehensive approach to the partial scan problem using implicit state enumeration. | Priyank Kalla, Maciej J. Ciesielski |
| 1997 | VTS | Testability of Sequential Circuits with Multi-Cycle False Path. | Priyank Kalla, Maciej J. Ciesielski |
| 1996 | ICCAD | Metamorphosis: state assignment by retiming and re-encoding. | Balakrishnan Iyer, Maciej J. Ciesielski |
| 1995 | DATE | Elimination of multi-cycle false paths by state encoding. | Zafar Hasan, Maciej J. Ciesielski |
| 1994 | ISCAS | Forum: Wave-pipelining: Is it Practical? | Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski |
| 1993 | VTS | Functional verification and simulation of FSM networks. | Zafar Hasan, Maciej J. Ciesielski |
| 1992 | ICCD | Finite State Machine Decomposition Using Multiway Partitioning. | Maya K. Yajnik, Maciej J. Ciesielski |
| 1991 | DAC | A Unified Approach to Input-Output Encoding for FSM State Assignment. | Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio |
| 1991 | DAC | Placement for Clock Period Minimization With Multiple Wave Propagation. | Donald A. Joy, Maciej J. Ciesielski |
| 1989 | ICCAD | PLA decomposition with generalized decoders. | Seiyang Yang, Maciej J. Ciesielski |
| 1989 | ICCD | Multiple-valued Boolean minimization based on graph coloring. | Maciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski |
| 1982 | DAC | An analytical method for compacting routing area in integrated circuits. | Maciej J. Ciesielski, Edwin Kinnen |
| 1981 | DAC | An optimum layer assignment for routing in ICs and PCBs. | Maciej J. Ciesielski, Edwin Kinnen |