Masahiko Yoshimoto
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
39
Venues
15
Active years
1995–2018
Best venue rank
C
Where they publish
Papers
39 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ISCAS | Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. | Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2017 | ASPDAC | A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. | Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori |
| 2016 | BIBE | Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis. | Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2016 | IOLTS | An soft error propagation analysis considering logical masking effect on re-convergent path. | Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2015 | ASPDAC | A 14A ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems. | Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2015 | ASPDAC | A negative-resistance sense amplifier for low-voltage operating STT-MRAM. | Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii |
| 2015 | IOLTS | An accurate soft error propagation analysis technique considering temporal masking disablement. | Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2015 | ISCAS | A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. | Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto |
| 2014 | ASPDAC | Normally-off technologies for healthcare appliance. | Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Yoshikazu Fujimori |
| 2014 | ISCAS | A 6T-4C shadow memory using plate line and word line boosting. | Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | ASPDAC | A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. | Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | ASPDAC | A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. | Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | ASPDAC | A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. | Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | BIBE | Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system. | Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | ICASSP | A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection. | Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2012 | APSEC | Implementing Virtual Agent as an Interface for Smart Home Voice Control. | Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2012 | IOLTS | Neutron-induced soft error rate estimation for SRAM using PHITS. | Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2012 | ISCAS | A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping. | Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi |
| 2012 | ISLPED | A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. | Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | DSD | A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. | Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | DSN | Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. | Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | ICCCN | Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. | Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi |
| 2011 | IOLTS | Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. | Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | ISCAS | A 40-nm 640-m | Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi |
| 2010 | FPL | Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. | Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2010 | ISCAS | Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. | Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi |
| 2010 | ISCAS | Intelligent ubiquitous sensor network for sound acquisition. | Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi |
| 2010 | ISCAS | Parallel-processing VLSI architecture for mixed integer linear programming. | Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2010 | ISLPED | 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. | Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2009 | Interspeech | Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. | Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2009 | VLSID | A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2008 | ISCAS | A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. | Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2007 | ASPDAC | Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. | Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2007 | WCNC | Delay Guarantee and Service Interval Optimization for HCCA in IEEE 802.11e WLANs. | Yuhi Higuchi, Augusto Foronda, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada |
| 2006 | ISLPED | A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. | Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2004 | ASPDAC | A sub-mW MPEG-4 motion estimation processor core for mobile video application. | Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto |
| 2001 | ICIP | An image sensor with fast extraction of objects' positions - rough vision processor. | Akira Watanabe, Osamu Tooyama, Masayuki Miyama, Masahiko Yoshimoto, Junichi Akita |
| 2000 | ISCAS | MPEG-2 4: 2: 2@HL encoder chip set. | Hidenori Sato, Hideo Ohira, Masahiko Kazayama, Ayako Harada, Masahiko Yoshimoto, Okikazu Tanno, Satoshi Kumaki, Kazuya Ishibara, Atsuo Hanami, Tetsuya Mutsumura |
| 1995 | ICASSP | A highly-parallel DSP architecture for image recognition. | Hiroyuki Kawai, Yoshitugu Inoue, Robert Streitenberger, Masahiko Yoshimoto |