Skip to content

Narayanan Vijaykrishnan

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

118

Venues

29

Active years

1996–2018

Best venue rank

A*

Where they publish

Papers

118 indexed papers, newest first.

YearVenueTitleAuthors
2018ISLPEDDual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems.Sandeep Krishna Thirumala, Arnab Raha, Hrishikesh Jayakumar, Kaisheng Ma, Narayanan Vijaykrishnan, Vijay Raghunathan, Sumeet Kumar Gupta
2011ISCAArchitecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2011ISCAA case for heterogeneous on-chip interconnects for CMPs.Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2010ASPDACA novel si-tunnel FET based SRAM design for ultra low-power 0.3V VJawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
2010DATEA GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching.Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan
2010DATEInvestigating the impact of NBTI on different power saving cache strategies.Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
2010FPLThermal Gradient Aware Clock Skew Scheduling for FPGAs.Sungmin Bae, Narayanan Vijaykrishnan
2009ASPDACA framework for estimating NBTI degradation of microarchitectural components.Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan
2009DATEExploiting clock skew scheduling for FPGA.Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan
2009HPCADesign and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2009MICROA case for dynamic frequency tuning in on-chip networks.Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2008DSNAnalysis and solutions to issue queue process variation.Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
2008ICCDComparative analysis of NBTI effects on low power and high performance flip-flops.Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie
2008ISCAMIRA: A Multi-layered On-Chip Interconnect Router Architecture.Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2008ISLPEDImpact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures.Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam
2007DATEAssessing carbon nanotube bundle interconnect for future FPGA architectures.Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
2007DATEThermally robust clocking schemes for 3D integrated circuits.Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
2007DATEWorking with process variation aware caches.Madhu Mutyam, Narayanan Vijaykrishnan
2007HOTIDesign of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das
2007ICCADVariation-aware task allocation and scheduling for MPSoC.Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan
2007ICCDFPGA routing architecture analysis under variations.Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan
2007ISCAA novel dimensionally-decomposed router for on-chip communication in 3D architectures.Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
2007VLSIDImpact of NBTI on FPGAs.Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin
2007VLSIDArchitecting Microprocessor Components in 3D Design Space.Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2006ASPDACObject duplication for improving reliability.Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2006DACFLAW: FPGA lifetime awareness.Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
2006DATEPriority scheduling in digital microfluidics-based biochips.Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin
2006DATEOn-chip bus thermal analysis and optimization.Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2006DSNExploring Fault-Tolerant Network-on-Chip Architectures.Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das
2006FCCMSwitch Box Architectures for Three-Dimensional FPGAs.Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman
2006ICCADThermal characterization and optimization in platform FPGAs.Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
2006ISCADesign and Management of 3D Chip Multiprocessors Using Network-in-Memory.Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir
2006MICROViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
2006VLSIDSEAT-LA: A Soft Error Analysis Tool for Combinational Logic.R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2006VLSIDA Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
2005ASPDACCluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
2005ASPDACLeakage control in FPGA routing fabric.Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
2005ASPDACDesigning reliable circuit in the presence of soft errors.Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2005ASPDACLow-leakage robust SRAM cell design for sub-100nm technologies.Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie
2005DACExploring technology alternatives for nano-scale FPGA interconnects.Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin
2005DACA low latency router supporting adaptivity for on-chip interconnects.Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das
2005DATECompiler-Directed Instruction Duplication for Soft Error Detection.Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2005DATEThermal-Aware Task Allocation and Scheduling for Embedded Systems.Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2005DATEHotspot Prevention Through Runtime Reconfiguration in Network-On-Chip.Greg M. Link, Narayanan Vijaykrishnan
2005DATESimultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures.Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
2005DATELeakage-Aware Interconnect for On-Chip Network.Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2005DATEPower Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach.Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie
2005FPGAEfficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
2005ICCDTemperature-Aware Voltage Islands Architecting in System-on-Chip Design.Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
2005ICCDThree-Dimensional Cache Design Exploration Using 3DCacti.Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2005ITCSoft errors: is the concern for soft-errors overblown?Narayanan Vijaykrishnan
2005VLSIDA Nanosensor Array-Based VLSI Gas Discriminator.Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin
2005VLSIDDetecting SEU-Caused Routing Errors in SRAM-Based FPGAs.E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
2005VLSIDImplementing LDPC Decoding on Network-on-Chip.Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
2005VLSIDInfluence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2005VLSIDAccurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang
2004DATEScheduling Reusable Instructions for Power Reduction.Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
2004DATEA Crosstalk Aware Interconnect with Variable Cycle Transmission.Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2004FPGAReducing leakage energy in FPGAs using region-constrained placement.Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
2004FPLA Dual-VAman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
2004HPCAExploring Wakeup-Free Instruction Scheduling.Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin
2004ICASSPEfficient VLSI implementation of inverse discrete cosine transform [image coding applications].Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
2004ICCADAnalyzing software influences on substrate noise: an ADC perspective.Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin
2004ICCADImproving soft-error tolerance of FPGA configuration bits.Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
2004ICCDThermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2004ISLPEDSoft error and energy consumption interactions: a data cache perspective.Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2004VLSIDDesigning Leakage Aware Multipliers.M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan
2004VLSIDAn Architecture for Motion Estimation in the Transform Domain.Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne H. Wolf
2004VLSIDEmbedded Hardware Face Detection.Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne H. Wolf
2003DACImplications of technology scaling on leakage reduction techniques.Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
2003DATEMasking the Energy Behavior of DES Encryption.Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang
2003DATECompiler Support for Reducing Leakage Energy Consumption.Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
2003DSDCCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif
2003ICCADAdapative Error Protection for Energy Efficiency.Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2003ICCDReducing dTLB Energy Through Dynamic Resizing.Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan
2003ISLPEDExploiting program hotspots and code sequentiality for instruction cache leakage management.Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
2003ISLPEDOn load latency in low-power caches.Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John
2003ISLPEDEstimating influence of data layout optimizations on SDRAM energy consumption.Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin
2003ISLPEDEnergy optimization techniques in cluster interconnects.Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das
2003ISPASSInterplay of energy and performance for disk arrays running transaction processing workloads.Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke, Narayanan Vijaykrishnan, Mary Jane Irwin
2003OOPSLAHeap compression for memory-constrained Java environments.Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Bernd Mathiske, Mario Wolczko
2003VLSIDAnalyzing Soft Errors in Leakage Optimized SRAM Design.Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin
2002ASPLOSUnderstanding and improving operating system effects in control flow prediction.Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio
2002DACScheduler-based DRAM energy management.Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2002DATEA Complete Phase-Locked Loop Power Consumption Model.David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
2002DATEPower-Efficient Trace Caches.Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2002DATEEAC: A Compiler Framework for High-Level Energy Estimation and Optimization.Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
2002HPCATuning Garbage Collection in an Embedded Java Environment.Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko
2002HPCAUsing Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach.Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John
2002ICCDImpact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes.David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, Grant McFarland
2002MICROCompiler-directed instruction cache leakage optimization.Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2002VLSIDCompiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories.Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu
2002VLSIDEvaluating Run-Time Techniques for Leakage Power Reduction.David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
2001CASESEnergy-efficient instruction cache using page-based placement.Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2001DACDynamic Management of Scratch-Pad Memory Space.Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
2001HPCADRAM Energy Management Using Software and Hardware Directed Power Mode Control.Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
2001ICCDA Framework for Energy Estimation of VLIW Architecture.Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2001ICCDUse of Local Memory for Efficient Java Execution.Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2001ISLPEDPower-aware partitioned cache architectures.Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali
2001MICROExploiting VLIW schedule slacks for dynamic and leakage energy reduction.Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai
2001PLDIMorphable Cache Architectures: Potential Benefits.Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jagannathan Ramanujam
2001VLSIDFormulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks.David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
2001VLDBAnalyzing energy behavior of spatial access methods for memory-resident data.Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Sudhanva Gurumurthi
2000CASESEnergy-oriented compiler optimizations for partitioned memory architectures.Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2000DACInfluence of compiler optimizations on system power.Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye
2000DACThe design and use of simplepower: a cycle-accurate energy estimation tool.Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2000HiPCData Organization and Retrieval on Parallel Air Channels.J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, S. Boonsiriwattanakul
2000HiPCEnergy-Aware Instruction Scheduling.Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2000HPCAArchitectural Issues in Java Runtime Systems.Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam
2000ISCAEnergy-driven integrated hardware-software optimizations using SimplePower.Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye
2000ICSUsing complete system simulation to characterize SPECjvm98 benchmarks.Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Jyotsna Sabarinathan, Anupama Murthy
2000ISLPEDMemory system energy (poster session): influence of hardware-software optimizations.G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
1999VLSIDEnergy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan
1998ECOOPObject-Oriented Architectural Support for a Java Processor.Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla
1996ICCDA VLSI array architecture with dynamic frequency clocking.N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
1996ICIPDFLAP: a dynamic frequency linear array processor.Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar
1996ICPRA dynamic frequency linear array processor for image processing.N. Ranganathan, N. Bhavanishankar, Narayanan Vijaykrishnan
1996VLSIDSUBGEN: a genetic approach for subcircuit extraction.Narayanan Vijaykrishnan, N. Ranganathan