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Russell Tessier

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

63

Venues

18

Active years

1993–2024

Best venue rank

A*

Where they publish

Papers

63 indexed papers, newest first.

YearVenueTitleAuthors
2024ETSReliability and Security of AI Hardware.Dennis Gnad, Martin Gotthard, Jonas Krautter, Angeliki Kritikakou, Vincent Meyers, Paolo Rech, Josie E. Rodriguez Condia, Annachiara Ruospo, Ernesto Snchez, Fernando Fernandes dos Santos, Olivier Sentieys, Mehdi B. Tahoori, Russell Tessier, Marcello Traiola
2024IGARSSSNOWWI: A Three-Frequency InSAR for Snow Science Applications.Paul Siqueira, Marc Closa Tarrs, Max Adam, Eric Sutherland, Joseph Maloyan, Takuya Seaver, Russell Tessier, Leung Tsang, Firoz Kanti Borah, H. P. Marshall, Elias Deeb, Gordon Farquharson
2024IGARSSFirst Results From a Dual Ku- and C-Band Airborne SAR for Snowpack Measurements.Marc Closa Tarrs, Paul Siqueira, J. Max Adam, Eric Sutherland, Joseph Maloyan, Takuya Seaver, Russell Tessier, Leung Tsang, Firoh Borah, HP Marshall, Elias Deeb, Gordon Farquharson
2023DATEA Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs.Shanquan Tian, Shayan Moini, Daniel E. Holcomb, Russell Tessier, Jakub Szefer
2023DDECSA Lightweight Intrusion Detection System against IoT Memory Corruption Attacks.Mohamed El Bouazzati, Russell Tessier, Philippe A. Tanguy, Guy Gogniat
2022FCCMPrecise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs.Xiang Li, Russell Tessier, Daniel E. Holcomb
2021DATERemote Power Side-Channel Attacks on BNN Accelerators in FPGAs.Shayan Moini, Shanquan Tian, Daniel E. Holcomb, Jakub Szefer, Russell Tessier
2021FCCMRemote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs.Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, Russell Tessier, Jakub Szefer
2020FPLPower Wasting Circuits for Cloud FPGA Attacks.George Provelengios, Daniel E. Holcomb, Russell Tessier
2020RSPNestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks.Xuzhi Zhang, Narendra Prabhu, Russell Tessier
2019FPGACharacterization of Long Wire Data Leakage in Deep Submicron FPGAs.George Provelengios, Chethan Ramesh, Shivukumar B. Patil, Ken Eguro, Russell Tessier, Daniel E. Holcomb
2019FPLCharacterizing Power Distribution Attacks in Multi-User FPGA Environments.George Provelengios, Daniel E. Holcomb, Russell Tessier
2019ISCASClosed-Loop Proportion-Derivative Control of Suppressing Seizures in a Neural Mass Model.Lijuan Xia, Ahmed Soltan, Xuzhi Zhang, Andrew Jackson, Russell Tessier, Patrick Degenaar
2018FCCMA Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip.Shivukumar B. Patil, Tianqi Liu, Russell Tessier
2018FCCMFPGA Side Channel Attacks without Physical Access.Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sbastien Pillement, Daniel E. Holcomb, Russell Tessier
2018FPLLynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping.Jonathan Dchelotte, Russell Tessier, Dominique Dallet, Jrmie Crenne
2017FCCMEnergy Efficient Loop Unrolling for Low-Cost FPGAs.Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier
2017FCCMScalable Network Function Virtualization for Heterogeneous Middleboxes.Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier
2016FPLEffects of I/O routing through column interfaces in embedded FPGA fabrics.Christophe Huriaux, Olivier Sentieys, Russell Tessier
2016FPLImproving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.Shrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb
2015DATEHardware-assisted code obfuscation for FPGA soft microprocessors.Meha Kainth, Lekshmi Krishnan, Chaitra Narayana, Sandesh Gubbi Virupaksha, Russell Tessier
2015FCCMProtecting against Cryptographic Trojans in FPGAs.Pawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux, Russell Tessier
2015FPLAdaptive MRAM-based CGRAs.Xiaobin Liu, Tedy Thomas, Alan Boguslawski, Russell Tessier
2014DACSystem-Level Security for Network Processors with Hardware Monitors.Kekai Hu, Tilman Wolf, Thiago Teixeira, Russell Tessier
2014FCCMFPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions.Christophe Huriaux, Olivier Sentieys, Russell Tessier
2014FPLFPGA architecture support for heterogeneous, relocatable partial bitstreams.Christophe Huriaux, Olivier Sentieys, Russell Tessier
2013DACHigh-performance hardware monitors to protect network processors from data plane attacks.Harikrishnan Chandrikakutty, Deepak Unnikrishnan, Russell Tessier, Tilman Wolf
2013DATEFPGA latency optimization using system-level transformations and DFG restructuring.Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier
2013DATERun-time probabilistic detection of miscalibrated thermal sensors in many-core systems.Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier
2012ICCADCollaborative calibration of on-chip thermal sensors using performance counters.Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson
2011FPLA Dynamically-Reconfigurable Phased Array Radar Processing System.Emmanuel Seguin, Russell Tessier, Eric J. Knapp, Robert W. Jackson
2011VTCEvaluation of the Universal Geocast Scheme for VANETs.Ben Bovee, Mohammad Nekoui, Hossein Pishro-Nik, Russell Tessier
2010DATEMulticore soft error rate stabilization using adaptive dual modular redundancy.Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier
2010FPGAScalable network virtualization using FPGAs.Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jrmie Crenne, Lixin Gao, Russell Tessier
2010SIGCOMMCustomizing virtual networks with partial FPGA reconfiguration.Dong Yin, Deepak Unnikrishnan, Yong Liao, Lixin Gao, Russell Tessier
2009DATEA monitor interconnect and support subsystem for multicore processors.Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier
2009FCCMApplication Specific Customization and Scalability of Soft Multiprocessors.Deepak Unnikrishnan, Jia Zhao, Russell Tessier
2009FPGACMOS vs Nano: comrades or rivals?Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, Andr DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
2009NSSDesign of a Secure Router System for Next-Generation Networks.Tilman Wolf, Russell Tessier
2009RSPAn Interactive Approach to Timing Accurate PCI-X Simulation.Kevin Andryc, Russell Tessier, Patrick Kelly
2007FCCMEstablishing Chain of Trust in Reconfigurable Hardware.Thomas Eisenbarth, Tim Gneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier
2007FPGAPower-aware FPGA logic synthesis using binary decision diagrams.Kevin Oo Tinmaung, David Howland, Russell Tessier
2006FPGAAn adaptive Reed-Solomon errors-and-erasures decoder.Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier
2006FPGAPower-aware RAM mapping for FPGA embedded memory blocks.Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy
2005IGARSSSalient features of radar nodes of the first generation NetRad System.Francesc Junyent, Venkatachalam Chandrasekar, David J. McLaughlin, Stephen J. Frasier, Edin Insanic, Razi Ahmed, Nitin Bharadwaj, Eric J. Knapp, Luko Krnan, Russell Tessier
2004FCCMA Dynamically-Reconfigurable, Power-Efficient Turbo Decoder.Jian Liang, Russell Tessier, Dennis Goeckel
2003FCCMFloating Point Unit Generation and Evaluation for FPGAs.Jian Liang, Russell Tessier, Oskar Mencer
2003FCCMAdaptive Fault Recovery for Networked Reconfigurable Systems.Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier
2003ICIPAdaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.Andrew Laffely, Jian Liang, Russell Tessier, Wayne P. Burleson
2003IGARSSFirst observations with the UMass dual-beam InSAR.William N. Junek, Arun Ramanathan, Gordon Farquharson, Stephen J. Frasier, Russell Tessier, David J. McLaughlin, Mark A. Sletten, Jakov V. Toporkov
2002FPGAA dynamically reconfigurable adaptive viterbi decoder.Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson
2002FPLThe Integration of SystemC and Hardware-Assisted Verification.Ramaswamy Ramaswamy, Russell Tessier
2001DACStatic Scheduling of Multiple Asynchronous Domains For Functional Verification.Murali Kudlugi, Charles Selvidge, Russell Tessier
2001ICASSPDynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power.Wayne P. Burleson, Russell Tessier, Dennis Goeckel, Sriram Swaminathan, Prashant Jain, Jeongseon Euh, Subramanian Venkatraman, Vidhya Thyagarajan
2001ICCADStatic Scheduling of Multi-Domain Memories For Functional Verification.Murali Kudlugi, Charles Selvidge, Russell Tessier
2001ITCBIST-based delay path testing in FPGA architectures.Ian G. Harris, Premachandran R. Menon, Russell Tessier
2000DACInterconnect testing in cluster-based FPGA architectures.Ian G. Harris, Russell Tessier
2000FPGATolerating operational faults in cluster-based FPGAs.Vijay Lakamraju, Russell Tessier
2000FPLArea-Optimized Technology Mapping for Hybrid FPGAs.Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier
2000FPLBalancing Logic Utilization and Area Efficiency in FPGAs.Russell Tessier, Heather Giza
2000ICCADDiagnosis of Interconnect Faults in Cluster-Based FPGA Architectures.Ian G. Harris, Russell Tessier
1999RSPIncremental Compilation for Logic Emulation.Russell Tessier
1993ICSThe NuMesh: A Modular, Scalable Communications Substrate.Steve Ward, Karim Abdalla, Rajeev Dujari, Michael Fetterman, Frank Honor, Ricardo Jenez, Philippe Laffont, Kenneth Mackenzie, Chris Metcalf, Milan Minsky, John Nguyen, John Pezaris, Gill A. Pratt, Russell Tessier