| 2026 | ASPDAC | Synthesis of CFET Standard Cells Utilizing Backside Interconnects Towards Improving Pin Accessibility. | Hyunbum Park, Taewhan Kim |
| 2026 | ASPDAC | ML-driven Design Technology Co-Optimization Framework for Advanced Technology Nodes. | Hyunbae Seo, Handong Cho, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim |
| 2026 | ASPDAC | Enhancing Pin Accessibility Through Pin Pattern Migration and Optimization Across Cell Boundaries. | Hyunbae Seo, Sehyeon Chung, Taewhan Kim |
| 2026 | DATE | Reshaping Bayesian Optimization for Design Space Optimization Towards Accurate and Irredundant Evaluation in EDA Tool Parameter Exploration. | Chanhee Jeon, Taewhan Kim |
| 2026 | DATE | Consolidating ML-driven Early IR-drop Mitigation for Fast and Reliable IR-drop Closure. | Munwon Lee, Chanhee Jeon, Taewhan Kim |
| 2025 | AAAI | ViPCap: Retrieval Text-Based Visual Prompts for Lightweight Image Captioning. | Taewhan Kim, Soeun Lee, Si-Woo Kim, Dong-Jin Kim |
| 2025 | ASPDAC | PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. | Eunsol Jeong, Taewhan Kim, Heechun Park |
| 2025 | CVPR | CheckManual: A New Challenge and Benchmark for Manual-based Appliance Manipulation. | Yuxing Long, Jiyao Zhang, Mingjie Pan, Tianshu Wu, Taewhan Kim, Hao Dong |
| 2025 | DAC | Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells. | Jaehoon Ahn, Taewhan Kim |
| 2025 | DAC | Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery. | Sehyeon Chung, Hyun-chul Hwang, Byung-Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim |
| 2025 | ICCAD | Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing. | Jaehoon Ahn, Sehyeon Chung, Taewhan Kim |
| 2025 | ICCAD | Synthesis of Standard Cells of Minimum Delay. | Sehyeon Chung, Hyunbae Seo, Taewhan Kim |
| 2025 | ICCD | Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques. | Yeongyeong Shin, Sehyeon Chung, Taewhan Kim |
| 2025 | ICCD | Threshold Voltage Tuning Technique for Leakage Power Recovery. | Jaejoon Yoon, Taewhan Kim |
| 2025 | IROS | ManipGPT: Is Affordance Segmentation by Large Vision Models Enough for Articulated Object Manipulation? | Taewhan Kim, Hojin Bae, Zeming Li, Xiaoqi Li, Iaroslav Ponomarenko, Ruihai Wu, Hao Dong |
| 2025 | ISLPED | Simultaneous Optimization of Placement Legalization and Multi-bit Flip-flop Allocation in Physical Design Automation. | Seoyoung Bang, Taewhan Kim |
| 2024 | DAC | Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. | Jooyeon Jeong, Taewhan Kim |
| 2024 | DAC | Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology. | Suwan Kim, Taewhan Kim |
| 2024 | DATE | Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. | Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim |
| 2024 | DATE | BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. | Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim |
| 2024 | EMNLP | IFCap: Image-like Retrieval and Frequency-based Entity Filtering for Zero-shot Captioning. | Soeun Lee, Si-Woo Kim, Taewhan Kim, Dong-Jin Kim |
| 2024 | ICCAD | Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. | Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim |
| 2024 | ISCAS | Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing. | Hwapyong Kim, Taewhan Kim |
| 2023 | DATE | DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. | Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim |
| 2023 | DATE | Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. | Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim |
| 2023 | ICCAD | Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops. | Suwan Kim, Taewhan Kim |
| 2023 | ISCAS | Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating. | Sora Park, Taewhan Kim |
| 2023 | ISLPED | Machine Learning Driven Synthesis of Clock Gating. | Doyeon Won, Soomin Kim, Taewhan Kim |
| 2022 | DATE | A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. | Eunsol Jeong, Heechun Park, Taewhan Kim |
| 2022 | DATE | Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model. | Suwan Kim, Taewhan Kim |
| 2022 | ICCAD | Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. | Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim |
| 2022 | ICCAD | Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells. | Soomin Kim, Taewhan Kim |
| 2022 | ISCAS | Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops. | Soomin Kim, Taewhan Kim |
| 2022 | ISCAS | Selective Clock Gating Based on Comprehensive Power Saving Analysis. | Sora Park, Taewhan Kim |
| 2022 | ISCAS | Improving Pin Accessibility of Standard Cells Through Fin Depopulation. | Doyeon Won, Taewhan Kim |
| 2022 | ISLPED | Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. | Sehyeon Chung, Jooyeon Jeong, Taewhan Kim |
| 2022 | ISLPED | Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. | Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park |
| 2021 | ASPDAC | Boosting Pin Accessibility Through Cell Layout Topology Diversification. | Suwan Kim, Kyeongrok Jo, Taewhan Kim |
| 2021 | DATE | Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks. | Jongsung Kang, Taewhan Kim |
| 2021 | ICCAD | Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis. | Kyeonghyeon Baek, Taewhan Kim |
| 2021 | ICCD | Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis. | Kyeongrok Jo, Taewhan Kim |
| 2020 | ASPDAC | Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. | Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi |
| 2020 | ASPDAC | Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. | Jeongwoo Heo, Taewhan Kim |
| 2020 | DATE | Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks. | Byungmin Ahn, Taewhan Kim |
| 2020 | ISLPED | Steady state driven power gating for lightening always-on state retention storage. | Taehwan Kim, Gyoung-Hwan Hyun, Taewhan Kim |
| 2019 | ICCAD | Flip-flop State Driven Clock Gating: Concept, Design, and Methodology. | Gyoung-Hwan Hyun, Taewhan Kim |
| 2019 | ICCAD | Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits. | Gyoung-Hwan Hyun, Taewhan Kim |
| 2018 | ASPDAC | Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. | Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi |
| 2018 | DATE | Structure optimizations of neuromorphic computing architectures for deep neural network. | Heechun Park, Taewhan Kim |
| 2018 | ICCAD | Design and algorithm for clock gating and flip-flop co-optimization. | Giyoung Yang, Taewhan Kim |
| 2017 | ASPDAC | Algorithm for synthesis and exploration of clock spines. | Youngchan Kim, Taewhan Kim |
| 2017 | ICCAD | Switch cell optimization of power-gated modern system-on-chips. | Dongyoun Yi, Taewhan Kim |
| 2016 | ASPDAC | Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. | Deokjin Joo, Taewhan Kim |
| 2016 | ASPDAC | Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. | Hyoungseok Moon, Taewhan Kim |
| 2016 | ICCAD | Allocation of multi-bit flip-flops in logic synthesis for power optimization. | Dongyoun Yi, Taewhan Kim |
| 2015 | ASPDAC | Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. | Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim |
| 2015 | ASPDAC | Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. | Juyeon Kim, Taewhan Kim |
| 2015 | ICCAD | Synthesis for Power-Aware Clock Spines. | Hyungjung Seo, Juyeon Kim, Minseok Kang, Taewhan Kim |
| 2014 | DATE | Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs. | Kitae Park, Geunho Kim, Taewhan Kim |
| 2013 | DAC | An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. | Juyeon Kim, Deokjin Joo, Taewhan Kim |
| 2013 | ICCAD | Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. | Heechun Park, Taewhan Kim |
| 2012 | ASPDAC | Algorithm for synthesizing design context-aware fast carry-skip adders. | Kiyoung Kim, Taewhan Kim |
| 2011 | ASPDAC | A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. | Yongho Lee, Taewhan Kim |
| 2011 | ASPDAC | An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. | Kyoung-Hwan Lim, Taewhan Kim |
| 2011 | DAC | WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. | Deokjin Joo, Taewhan Kim |
| 2010 | ASPDAC | Clock tree embedding for 3D ICs. | Tak-Yung Kim, Taewhan Kim |
| 2010 | ASPDAC | Technique for controlling power-mode transition noise in distributed sleep transistor network. | Yongho Lee, Taewhan Kim |
| 2010 | DAC | Clock tree synthesis with pre-bond testability for 3D stacked IC designs. | Tak-Yung Kim, Taewhan Kim |
| 2010 | ICCAD | Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. | Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim |
| 2009 | ASPDAC | Timing variation-aware task scheduling and binding for MPSoC. | HaNeul Chon, Taewhan Kim |
| 2009 | DAC | Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. | Hochang Jang, Taewhan Kim |
| 2009 | ICCD | Timing variation-aware high-level synthesis considering accurate yield computation. | Jongyoon Jung, Taewhan Kim |
| 2008 | ASPDAC | Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. | Byunghyun Lee, Taewhan Kim |
| 2008 | ICCAD | Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. | Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim |
| 2008 | ICCAD | Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. | Yesin Ryu, Taewhan Kim |
| 2008 | ISLPED | Power-gating-aware high-level synthesis. | Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin |
| 2007 | DAC | Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. | Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim |
| 2007 | ICCAD | Timing variation-aware high-level synthesis. | Jongyoon Jung, Taewhan Kim |
| 2007 | ISCAS | Address Code Optimization Exploiting Code Scheduling in DSP Applications. | Zhenmin Li, Taewhan Kim |
| 2007 | RTCSA | Temperature-Aware Compilation for VLIWProcessors. | Benjamin Carrin Schfer, Yongho Lee, Taewhan Kim |
| 2006 | DATE | A systematic IP and bus subsystem modeling for platform-based system design. | Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim |
| 2006 | RTCSA | Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. | Taewhan Kim |
| 2005 | DAC | DC-DC converter-aware power management for battery-operated embedded systems. | Yongseok Choi, Naehyuck Chang, Taewhan Kim |
| 2005 | DAC | Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. | Jungeun Kim, Taewhan Kim |
| 2005 | ICCAD | Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. | Jaewon Seo, Taewhan Kim, Nikil D. Dutt |
| 2004 | ASPDAC | Resource-constrained low-power bus encoding with crosstalk delay elimination. | Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim |
| 2004 | ASPDAC | Memory access driven storage assignment for variables in embedded system design. | Yoonseo Choi, Taewhan Kim |
| 2004 | ASPDAC | An integrated approach to timing-driven synthesis and placement of arithmetic circuits. | Keoncheol Shin, Taewhan Kim |
| 2004 | DAC | Memory access scheduling and binding considering energy minimization in multi-bank memory systems. | Chun-Gi Lyuh, Taewhan Kim |
| 2004 | DAC | Profile-based optimal intra-task voltage scheduling for hard real-time applications. | Jaewon Seo, Taewhan Kim, Ki-Seok Chung |
| 2003 | DAC | Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. | Yoonseo Choi, Taewhan Kim |
| 2003 | DAC | Optimal voltage allocation techniques for dynamically variable voltage processors. | Woo-Cheol Kwon, Taewhan Kim |
| 2003 | ICCAD | Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. | Junhyung Um, Taewhan Kim |
| 2003 | ISCAS | An efficient inverse multiplier/divider architecture for cryptography systems. | Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim |
| 2002 | DAC | Address assignment combined with scheduling in DSP code generation. | Yoonseo Choi, Taewhan Kim |
| 2002 | DAC | An integrated algorithm for memory allocation and assignment in high-level synthesis. | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda |
| 2002 | DAC | Layout-aware synthesis of arithmetic circuits. | Junhyung Um, Taewhan Kim |
| 2002 | ICCAD | Coupling-aware high-level interconnect synthesis for low power. | Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim |
| 2002 | ICCAD | Layout-driven resource sharing in high-level synthesis. | Junhyung Um, Jae-Hoon Kim, Taewhan Kim |
| 2002 | ISCAS | An efficient low-power binding algorithm in high-level synthesis. | Yoonseo Choi, Taewhan Kim |
| 2002 | ISCAS | Address code optimization using code scheduling for digital signal processors. | Yoonseo Choi, Taewhan Kim |
| 2002 | ISCAS | Enhanced bus invert encodings for low-power. | Unni Narayanan, Ki-Seok Chung, Taewhan Kim |
| 2002 | ISCAS | Memory exploration utilizing scheduling effects in high-level synthesis. | Jaewon Seo, Taewhan Kim |
| 2001 | ASPDAC | Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. | Youngtae Kim, Taewhan Kim |
| 2001 | DAC | A Static Estimation Technique of Power Sensitivity in Logic Circuits. | Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu |
| 2001 | ICCAD | A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. | Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung |
| 2001 | ICCAD | An Integrated Data Path Optimization for Low Power Based on Network Flow Method. | Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu |
| 2000 | ASPDAC | A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). | Taewhan Kim, Junhyung Um |
| 2000 | DAC | A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. | Junhyung Um, Taewhan Kim, C. L. Liu |
| 2000 | ICCAD | Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. | Sungpack Hong, Taewhan Kim |
| 2000 | ICCAD | A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. | Gernot Koch, Taewhan Kim, Reiner Genevriere |
| 1999 | ICCAD | Optimal allocation of carry-save-adders in arithmetic optimization. | Junhyung Um, Taewhan Kim, C. L. Liu |
| 1998 | DAC | Arithmetic Optimization Using Carry-Save-Adders. | Taewhan Kim, William Jao, Steven W. K. Tjiang |
| 1993 | DAC | Utilization of Multiport Memories in Data Path Synthesis. | Taewhan Kim, C. L. Liu |
| 1991 | ICCAD | A Scheduling Algorithm for Conditional Resource Sharing. | Taewhan Kim, Jane W.-S. Liu, C. L. Liu |