| 2000 | A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). | Taewhan Kim, Junhyung Um |
| 2000 | Delay-optimal wiring plan for the microprocessor of high performance computing machines. | Jun Kikuchi, Tetsuo Sasaki, Tohru Hashimoto, Kazuhisa Miyamoto |
| 2000 | Analytical minimization of half-perimeter wirelength. | Andrew A. Kennings, Igor L. Markov |
| 2000 | Gate-level aged timing simulation methodology for hot-carrier reliability assurance. | Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu |
| 2000 | A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. | Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano |
| 2000 | 300MHz design methodology of VU for emotion synthesis. | Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu |
| 2000 | An analytic calculation method for delay time of RC-class interconnects. | W. K. Kal, S. Y. Kim |
| 2000 | A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. | Young-Deuk Jeon, Byeong-Lyeol Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee |
| 2000 | Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. | Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi |
| 2000 | A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. | Kazuhito Ito |
| 2000 | Clock design of 300MHz 128-bit 2-way superscalar microprocessor. | Fujio Ishihara, Christian Klinger, Ken-ichi Agawa |
| 2000 | Communicating logic: an alternative embedded stream processing paradigm. | Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada |
| 2000 | One language or more?: how can we design an SoC at a system level? | Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura |
| 2000 | A hardware simulation engine based on decision diagrams (short paper). | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno |
| 2000 | A new method for constructing IP level power model based on power sensitivity. | Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 2000 | A programmable built-in self-test core for embedded memories. | Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu |
| 2000 | A sigma-delta modulation based BIST scheme for mixed-signal circuits. | Jiun-Lang Huang, Kwang-Ting Cheng |
| 2000 | A new approach to assembly software retargeting for microcontrollers. | Ing-Jer Huang, Dao-Zhen Chen |
| 2000 | A new CMAC neural network architecture and its ASIC realization. | Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang |
| 2000 | Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. | Jin-Hua Hong, Cheng-Wen Wu |
| 2000 | Symbolic debugging of globally optimized behavioral specifications. | Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou |
| 2000 | Fault models and test generation for IDDQ testing: embedded tutorial. | Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita |
| 2000 | KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. | Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger |
| 2000 | Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. | Jiangchun Gu, Zeyi Wang, Xianlong Hong |
| 2000 | Embedded tutorial: IC design technology for building system-on-a-chip. | Rajesh Gupta |