| 2000 | The enchancing of efficiency of the harmonic balance analysis by adaptation of preconditioner to circuit nonlinearity. | Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney |
| 2000 | A hybrid approach for core-based system-level power modeling. | Tony Givargis, Frank Vahid, Jrg Henkel |
| 2000 | Retargetable estimation scheme for DSP architecture selection. | Naji Ghazal, A. Richard Newton, Jan M. Rabaey |
| 2000 | Embedded tutorial: essential issues for IP reuse. | Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud |
| 2000 | Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). | Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa |
| 2000 | A method for linking process-level variability to system performances. | Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru |
| 2000 | An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines. | Riccardo Forth, Paul Molitor |
| 2000 | Superlog, a unified design language for system-on-chip. | Peter Flake, Simon J. Davidmann |
| 2000 | A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. | Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong |
| 2000 | Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. | Nong Fan, Viraphol Chaiyakul, Daniel Gajski |
| 2000 | embedded system design with multiple languages: embedded tutorial. | Rolf Ernst, Ahmed Amine Jerraya |
| 2000 | Compact yet high performance (CyHP) library for short time-to-market with new technologies. | Nguyen Minh Duc, Takayasu Sakurai |
| 2000 | Reuse and protection of intellectual property in the SpecC system. | Rainer Dmer, Daniel Gajski |
| 2000 | Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. | Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi |
| 2000 | Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. | Debatosh Debnath, Tsutomu Sasao |
| 2000 | Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. | Jason Cong, Songjie Xu |
| 2000 | Performance driven multiway partitioning. | Jason Cong, Sung Kyu Lim |
| 2000 | Edge separability based circuit clustering with application to circuit partitioning. | Jason Cong, Sung Kyu Lim |
| 2000 | Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. | Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu |
| 2000 | Power reduction by simultaneous voltage scaling and gate sizing. | Chunhong Chen, Majid Sarrafzadeh |
| 2000 | Monte-Carlo algorithms for layout density control. | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
| 2000 | A benchmark suite for substrate analysis. | Edoardo Charbon, Lus Miguel Silveira, Paolo Miliozzi |
| 2000 | Array allocation taking into account SDRAM characteristics. | Hong-Kai Chang, Youn-Long Lin |
| 2000 | On mixture density and maximum likelihood power estimation via expectation-maximization. | Ramamurti Chandramouli, Vamsi K. Srikantam |
| 2000 | Timing closure: the solution and its problems. | Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten |