| 2019 | Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems. | Luks Kohtka, Luks Nagy, Viera Stopjakov |
| 2019 | Analyzing and Optimizing the Dummy Rounds Scheme. | Stanislav Jerabek, Jan Schmidt |
| 2019 | Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. | Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen |
| 2019 | New categories of Safe Faults in a processor-based Embedded System. | Cemil Cem Grsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar |
| 2019 | Hash-based Pattern Matching for High Speed Networks. | Tomas Fukac, Jan Korenek |
| 2019 | Hybrid on-line self-test architecture for computational units on embedded processor cores. | Andrea Floridia, Gianmarco Mongano, Davide Piumatti, Ernesto Snchez |
| 2019 | FPGA-based SIFT implementation for wearable computing. | Attila Fejr, Zoltn Nagy, Jenny Benois-Pineau, Pter Szolgay, Aymar de Rugy, Jean-Philippe Domenger |
| 2019 | Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. | Mariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz |
| 2019 | A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider. | Hwann-Kaeo Chiou, Wei-Min Sung |
| 2019 | Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. | Ching-Hwa Cheng, Tang-Chieh Liu |
| 2019 | Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. | Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang |
| 2019 | On the in-field test of the GPGPU scheduler memory. | Stefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda |
| 2019 | Using Voters May Lead to Secret Leakage. | Jan Belohoubek, Petr Fiser, Jan Schmidt |
| 2019 | Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test. | F. Almeida, Paolo Bernardi, D. Calabrese, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli, Gulio Zoppi |
| 2018 | On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. | Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio |
| 2018 | Augmenting All Solution SAT Solving for Circuits with Structural Information. | Abraham Temesgen Tibebu, Grschwin Fey |
| 2018 | Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. | Alexander Sprenger, Sybille Hellebrand |
| 2018 | 2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. | Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz |
| 2018 | Self Vth-Compensating CMOS On-Chip Rectifier for Inductively Powered Implantable Medical Devices. | Miroslav Potocn, Viera Stopjakov, Martin Kovc |
| 2018 | A Rare Event Based Yield Estimation Methodology for Analog Circuits. | Izel Cagin Odabasi, Mustafa Berke Yelten, Engin Afacan, I. Faik Baskaya, Ali Emre Pusane, Gnhan Dndar |
| 2018 | Nonlinear Binary Codes and Their Utilization for Test. | Ondreg Novak |
| 2018 | Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology. | Luks Nagy, Daniel Arbet, Martin Kovc, Miroslav Potocn, Viera Stopjakov |
| 2018 | A Methodology to Verify Digital IP's within Mixed-Signal Systems. | Navaneetha Channiganathota Manjappa, Anselm Breitenreiter, Markus Ulbricht, Milos Krstic |
| 2018 | Contribution to Automated Generating of System Power-Management Specification. | Dominik Macko |
| 2018 | Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. | Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic |