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International Symposium on Design and Diagnostics of Electronic Circuits and Systems

DDECS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

1,124

2006–2026

Papers per year

200691 peak2026

DDECS papers

1,124 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2018Natural Language Based Power Domain Partitioning.David Lemma, Daniel Groe, Rolf Drechsler
2018Heuristic for Page-Based Incremental Reprogramming of Wireless Sensor Nodes.Kai Lehniger, Stefan Weidling, Mario Schlzel
2018Heap Queue: A Novel Efficient Hardware Architecture of MIN/MAX Queues for Real-Time Systems.Luks Kohtka, Viera Stopjakov
2018Software-Level TMR Approach for On-Board Data Processing in Space Applications.Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Grschwin Fey
2018Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA.Florian Huemer, Thomas Polzer, Andreas Steininger
2018Reliability-Aware Multi-Vth Domain Digital Design Assessment.Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen
2018Synthesis of Finite State Machines on Memristor Crossbars.Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio
2018Integrated Sensors for Early Breast Cancer Diagnostics.Omar Farag, Mariam Mohamed, Mohamed A. Abd El-Ghany, Klaus Hofmann
2018A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability.Seyed Hamid Fani, Ali Peiravi, Hooman Farkhani, Farshad Moradi
2018Intermittent Resistance Fault Detection at Board Level.Hassan Ebrahimi, Hans G. Kerkhoff
2018Modeling and Accelerated Mixed-Signal Simulation of a Control System.Sara Divanbeigi, Felix Winkler, Martin Bergen, Markus Olbrich
2018Design of Low-Bit Robust Analog-to-Digital Converters for Signals with Gaussian Distribution.Milan R. Dincic, Zoran H. Peric, Dragan B. Denic, Zoran Stamenkovic
2018Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing.Harshad Dhotre, Stephan Eggersgl, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
2018An Integrated Phase Shifting Frequency Synthesizer for Active Electronically Scanned Arrays.Giulio D'Amato, Giovanni Piccinni, Gianfranco Avitabile, Giuseppe Coviello, Claudio Talarico
2018An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test.Riccardo Cantoro, Luigi San Paolo, Matteo Sonza Reorda, Giovanni Squillero
2018Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells.Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar
2018QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
2018Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications.Daniel Arbet, Martin Kovc, Luks Nagy, Viera Stopjakov, Michal Sovcik
2018Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC.Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano
2017Improving combinational circuit resilience against soft errors via selective resource allocation.Tohid Taghizad Gogjeh Yaran, Suleyman Tosun
2017On the robustness of memristor based logic gates.Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, Mottaqiallah Taouil, Said Hamdioui
2017A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology.Michal Wolodzko, Wieslaw Kuzmicz
2017Towards approximation during test of Integrated Circuits.Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017A scalable technique to identify true critical paths in sequential circuits.Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
2017Formal Design Space Exploration for memristor-based crossbar architecture.Marcello Traiola, Mario Barbareschi, Alberto Bosio
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