| 2017 | Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology. | Michal Sovcik, Martin Kovc, Daniel Arbet, Viera Stopjakov |
| 2017 | Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. | Petr Socha, Vojtech Miskovsk, Hana Kubtov, Martin Novotn |
| 2017 | PMS2UPF: An automated transition from ESL to RTL power-intent specification. | Miroslav Siro, Dominik Macko, Katarna Jelemensk |
| 2017 | Cycle-accurate software modeling for RTL verification of embedded systems. | Michael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz |
| 2017 | Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. | Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic |
| 2017 | Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. | Patrick Russell, Jens Dge, Christoph Hoppe, Thomas B. Preuer, Peter Reichel, Peter Schneider |
| 2017 | An efficient physical design of fully-testable BDD-based circuits. | Andreas Rauchenecker, Robert Wille |
| 2017 | Structure-preserving modeling of safety-critical combinational circuits. | Feim Ridvan Rasim, Canan Kocar, Sebastian M. Sattler |
| 2017 | Body biasing for analog design: Practical experiences in 22 nm FD-SOI. | Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich |
| 2017 | Measuring metastability using a time-to-digital converter. | Thomas Polzer, Florian Huemer, Andreas Steininger |
| 2017 | Mealy-to-moore transformation. | Mustafa Ozgul, Florian Deeg, Sebastian M. Sattler |
| 2017 | Design for three-dimensional sound processor using high-level synthesis. | Saya Ohira, Tetsuya Matsumura |
| 2017 | Logic testing with test-per-clock pattern loading and improved diagnostic abilities. | Ondrej Novk, Zdenek Plva |
| 2017 | Analog front-end for precise human body temperature measurement. | Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz |
| 2017 | On hardware-based fault-handling in dynamically scheduled processors. | Felix Mhlbauer, Lukas Schrder, Mario Schlzel |
| 2017 | HLS design of a hardware accelerator for Homomorphic Encryption. | Asma Mkhinini, Paolo Maistri, Rgis Leveugle, Rached Tourki |
| 2017 | Rocket Queue: New data sorting architecture for real-time systems. | Luks Kohtka, Viera Stopjakov |
| 2017 | Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator. | Madis Kerner, Kalle Tammeme |
| 2017 | Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. | Matthias Kampmann, Sybille Hellebrand |
| 2017 | Firmware Update Manager: A remote firmware reprogramming tool for low-power devices. | Ondrej Kachman, Marcel Balz |
| 2017 | A novel architecture for LZSS compression of configuration bitstreams within FPGA. | Radek Isa, Jir Matousek |
| 2017 | Design and optimisation of NiTi pressure gauge. | Martin Hunek, Zdenek Plva |
| 2017 | Are XORs in logic synthesis really necessary? | Ivo Hlecek, Petr Fiser, Jan Schmidt |
| 2017 | Novel metrics for Analog Mixed-Signal coverage. | Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher |
| 2017 | Mapping abstract and concrete hardware models for design understanding. | Tino Flenker, Grschwin Fey |