| 2020 | Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. | Ayan Palchaudhuri, Anindya Sundar Dhar |
| 2020 | Rotary Register File: A Micro-Architectural Primitive on FPGA. | Reza Nakhjavani, Jianwen Zhu |
| 2020 | High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. | Hiroki Nakahara, Zhiqiang Que, Wayne Luk |
| 2020 | An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAs. | Jannatun Naher, Clay Gloster, Christopher C. Doss, Shrikant S. Jadhav |
| 2020 | SqueezeJet-3: An Accelerator Utilizing FPGA MPSoCs for Edge CNN Applications. | Panagiotis Mousouliotis, Ioannis Papaefstathiou, Loukas Petrou |
| 2020 | Early-stage Automated Identification Tool for Shared Accelerators. | Parnian Mokri, Mark Hempstead |
| 2020 | Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms. | Yuan Meng, Sanmukh R. Kuppannagari, Viktor K. Prasanna |
| 2020 | Accommodating Multi-Tenant FPGAs in the Cloud. | Joel Mandebi Mbongue, Christophe Bobda |
| 2020 | Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors. | Eric Matthews, Yuhui Gao, Lesley Shannon |
| 2020 | Power-hammering through Glitch Amplification - Attacks and Mitigation. | Kaspar Matas, Tuan Minh La, Khoa Dang Pham, Dirk Koch |
| 2020 | A Turbo Maximum-a-Posteriori Equalizer for Faster-than-Nyquist Applications. | Mohamed Omran Matar, Mrinmoy Jana, Jeebak Mitra, Lutz Lampe, Mieszko Lis |
| 2020 | FPGA Based High-Throughput Real-Time Feature Extraction for Modulation Classification. | Joshua Mack, Ali Akoglu |
| 2020 | Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs. | Alaa Maarouf, Nour El Droubi, Raghid Morcel, Hazem M. Hajj, Mazen A. R. Saghir, Haitham Akkary |
| 2020 | A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA. | Yukui Luo, Xiaolin Xu |
| 2020 | Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. | Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong |
| 2020 | Hierarchical Modelling of Generators in Design-Space Exploration. | Charles Lo, Paul Chow |
| 2020 | FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks. | Haoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson |
| 2020 | A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. | Ning Li, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2020 | Update Latency Optimization of Packet Classification for SDN Switch on FPGA. | Chenglong Li, Tao Li, Junnan Li, Zilin Shi, Baosheng Wang |
| 2020 | Improving the Availability of Secure Space Links through the Partial Reconfiguration of FPGAs. | Emmanuel Lesser |
| 2020 | Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs. | Ian Elmor Lang, Ziqiang Huang, Nachiket Kapre |
| 2020 | High Density 8-Bit Multiplier Systolic Arrays For Fpga. | Martin Langhammer, Sergey Gribok, Gregg Baeckler |
| 2020 | Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. | Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar |
| 2020 | An Efficient FPGA-based Architecture for Contractive Autoencoders. | Madis Kerner, Kalle Tammeme, Jaan Raik, Thomas Hollstein |
| 2020 | Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. | Akira Jinguji, Shimpei Sato, Hiroki Nakahara |