| 2016 | DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. | Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy |
| 2016 | Runtime Parameterizable Regular Expression Operators for Databases. | Zsolt Istvn, David Sidler, Gustavo Alonso |
| 2016 | KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. | Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix 10 FPGA. | Dana L. How, Sean Atsatt |
| 2016 | Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms. | Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars |
| 2016 | Evaluating Embedded FPGA Accelerators for Deep Learning Applications. | Gopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Vamsi Buddha, Nachiket Kapre |
| 2016 | A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment. | Tanja Harbaum, Mahmoud Seboui, Matthias Norbert Balzer, Jrgen Becker, Marc Weber |
| 2016 | GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator. | Jan Gray |
| 2016 | Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). | Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, Andr DeHon |
| 2016 | Accelerating Apache Spark Big Data Analysis with FPGAs. | Ehsan Ghasemi, Paul Chow |
| 2016 | Vertex-Centric Graph Processing on FPGA. | Nina Engelhardt, Hayden Kwok-Hay So |
| 2016 | High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two. | William Diehl, Kris Gaj |
| 2016 | Accelerating Equi-Join on a CPU-FPGA Heterogeneous Platform. | Ren Chen, Viktor K. Prasanna |
| 2016 | When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. | Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei |
| 2016 | The SMEM Seeding Acceleration for DNA Sequence Alignment. | Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu |
| 2016 | Two-Hit Filter Synthesis for Genomic Database Search. | Jordan A. Bradshaw, Rasha Karakchi, Jason D. Bakos |
| 2016 | P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. | Pavel Bencek, Viktor Pus, Hana Kubtov |
| 2016 | A LUT-Based Approximate Adder. | Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jrgen Teich |
| 2016 | Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC. | Amine Ait Si Ali, Xiaojun Zhai, Abbes Amira, Faycal Bensaali, Naeem Ramzan |
| 2016 | High Level Synthesis Based E-Nose System for Gas Applications. | Amine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar, Muhammad Hassan, Amine Bermak |
| 2016 | Reconfiguration Control Networks for TMR Systems with Module-Based Recovery. | Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong |
| 2016 | A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. | Ameer M. S. Abdelhadi, Guy G. F. Lemieux |
| 2015 | FPGA Design for PCANet Deep Learning Network. | Yuteng Zhou, Wei Wang, Xinming Huang |
| 2015 | Rapid Overlay Builder for Xilinx FPGAs. | Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux |
| 2015 | Offset Pipelined Scheduling: Conditional Branching for CGRAs. | Aaron Wood, Scott Hauck |