| 2015 | A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data Storages. | Dongyang Li, Qing Yang, Qingbo Wang, Cyril Guyot, Ashwin Narasimha, Dejan Vucinic, Zvonimir Bandic |
| 2015 | FPGA Acceleration of Recurrent Neural Network Based Language Model. | Sicheng Li, Chunpeng Wu, Hai Li, Boxun Li, Yu Wang, Qinru Qiu |
| 2015 | Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. | Cheng Liu, Hayden Kwok-Hay So |
| 2015 | Optimizing Residue Number Reverse Converters through Bitwise Arithmetic on FPGAs. | Bangtian Liu, Haohuan Fu, Lin Gan, Wenlai Zhao, Guangwen Yang |
| 2015 | Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. | Junyi Liu, Samuel Bayliss, George A. Constantinides |
| 2015 | Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs. | Aaron Landy, Greg Stitt |
| 2015 | An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures. | Jens Korinth, David de la Chevallerie, Andreas Koch |
| 2015 | Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area. | Farheen Fatima Khan, Andy Ye |
| 2015 | Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing. | Nachiket Kapre, Bibin Chandrashekaran, Harnhua Ng, Kirvy Teo |
| 2015 | Sparse Graph Processing with Soft-Processors. | Nachiket Kapre |
| 2015 | A Reconfigurable Multiclass Support Vector Machine Architecture for Real-Time Embedded Systems Classification. | Jason Kane, Robert Hernandez, Qing Yang |
| 2015 | Efficient Overlay Architecture Based on DSP Blocks. | Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell |
| 2015 | A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing. | Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin P. Hand, Robert Carlson, Emre Ozer |
| 2015 | Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors. | Gopalakrishna Hegde, Nachiket Kapre |
| 2015 | High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow Model. | Mohamed W. Hassan, Ahmed E. Helal, Yasser Y. Hanafy |
| 2015 | Estimating Soft Processor Soft Error Sensitivity through Fault Injection. | Nathan A. Harward, Michael R. Gardiner, Luke W. Hsiao, Michael J. Wirthlin |
| 2015 | Pipelined Genetic Propagation. | Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk |
| 2015 | Accelerating SpMV on FPGAs by Compressing Nonzero Values. | Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk |
| 2015 | Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. | Jeffrey B. Goeders, Steven J. E. Wilton |
| 2015 | High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis. | Matthias Gbel, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink |
| 2015 | Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. | Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Lujn |
| 2015 | A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs. | Jeremy Fowers, Joo-Young Kim, Doug Burger, Scott Hauck |
| 2015 | A Low-Latency, Low-Area Hardware Oblivious RAM Controller. | Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios N. Serpanos, Srinivas Devadas |
| 2015 | Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs. | Hongyuan Ding, Miaoqing Huang |
| 2015 | Adjustable-Cost Overlays for Runtime Compilation. | James Coole, Greg Stitt |