| 2015 | Functional Locking Modules for Design Protection of Intellectual Property Cores. | Brice Colombier, Lilian Bossuet |
| 2015 | Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. | Thiem Van Chu, Shimpei Sato, Kenji Kise |
| 2015 | A Novel High-Throughput Acceleration Engine for Read Alignment. | Yu-Ting Chen, Jason Cong, Jie Lei, Peng Wei |
| 2015 | Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. | Alban Bourge, Olivier Muller, Frdric Rousseau |
| 2015 | High-Level Debugging and Verification for FPGA-Based Multicore Architectures. | Oriol Arcas-Abella, Adrin Cristal, Osman S. Unsal |
| 2015 | Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. | Joo Andrade, Nithin George, Kimon Karras, David Novo, Vtor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falco Paiva Fernandes |
| 2015 | FIR Filter Based on Stochastic Computing with Reconfigurable Digital Fabric. | Mohammed Alawad, Mingjie Lin |
| 2015 | Modular SRAM-Based Binary Content-Addressable Memories. | Ameer M. S. Abdelhadi, Guy G. F. Lemieux |
| 2014 | A Fully-Pipelined FPGA Design for Tree-Reweighted Message Passing Algorithm. | Wenlai Zhao, Haohuan Fu, Guangwen Yang |
| 2014 | MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations. | Deheng Ye, Nachiket Kapre |
| 2014 | LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. | Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer |
| 2014 | High-Throughput and Low-Cost Hardware Accelerator for Privacy Preserving Publishing. | Fumito Yamaguchi, Hiroaki Nishi |
| 2014 | A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture. | Tian Xiang, Lei Zhao, Xi Jin, Tianqi Wang, Shaoping Chu, Cong Ma, Shubin Liu, Qi An, Xue Ben |
| 2014 | Image Signal Processors on FPGAs. | Di Wu, Andreas Moshovos |
| 2014 | Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. | Felix Winterstein, Samuel Bayliss, George A. Constantinides |
| 2014 | An Efficient Architecture for Floating-Point Eigenvalue Decomposition. | Xinying Wang, Joseph Zambreno |
| 2014 | Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq. | Kizheppatt Vipin, Suhaib A. Fahmy |
| 2014 | System-Level Retiming and Pipelining. | Girish Venkataramani, Yongfeng Gu |
| 2014 | Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. | Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux |
| 2014 | FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy. | David B. Thomas |
| 2014 | Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom. | Qingshan Tang, Matthieu Tuna, Habib Mehrez |
| 2014 | FPGA Implementation of Optical Flow Algorithm Based on Cost Aggregation. | Yu Tanabe, Tsutomu Maruyama |
| 2014 | A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution. | Hamed Tabkhi, Majid Sabbagh, Gunar Schirner |
| 2014 | Timing Fault Detection in FPGA-Based Circuits. | Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre |
| 2014 | Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization. | Siddhartha, Nachiket Kapre |