| 2020 | FTDL: An FPGA-tailored Architecture for Deep Learning Systems. | Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding |
| 2020 | Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. | Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang |
| 2020 | An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops. | Rupesh S. Shelar |
| 2020 | Closing Leaks: Routing Against Crosstalk Side-Channel Attacks. | Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic |
| 2020 | When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network. | Vladimir Rybalkin, Norbert Wehn |
| 2020 | LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. | Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong |
| 2020 | QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators. | Rachit Rajat, Yuan Meng, Sanmukh R. Kuppannagari, Ajitesh Srivastava, Viktor K. Prasanna, Rajgopal Kannan |
| 2020 | Scalable FPGA Median Filtering using Multiple Efficient Passes. | Oscar Rahnama, Tommaso Cavallari, Philip H. S. Torr, Stuart Golodetz |
| 2020 | What To Do With Datacenter FPGAs Besides Deep Learning. | Andrew Putnam |
| 2020 | Hardware Description Beyond Register-Transfer Level Languages. | Oron Port, Yoav Etsion |
| 2020 | High-Performance FPGA Network Switch Architecture. | Philippos Papaphilippou, Jiuxi Meng, Wayne Luk |
| 2020 | Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. | Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar |
| 2020 | Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration. | Yue Niu, Rajgopal Kannan, Ajitesh Srivastava, Viktor K. Prasanna |
| 2020 | Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2020 | FPGAs will Never be the Same Again: How the Newest FPGA Architectures are Totally Disrupting the Entire FPGA Ecosystem as We Know It. | Raymond X. Nijssen |
| 2020 | Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment. | Tuan D. A. Nguyen, Akash Kumar |
| 2020 | R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. | Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk |
| 2020 | Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree. | Parnian Mokri, Maziar Amiraskari, Yuelin Liu, Mark Hempstead |
| 2020 | A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. | Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai |
| 2020 | CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. | Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic |
| 2020 | Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations. | Rene Miedema, Georgios Smaragdos, Mario Negrello, Zaid Al-Ars, Matthias Mller, Christos Strydis |
| 2020 | FPGA / SoC Security: Arms Race in the Cloud. | Steven McNeil |
| 2020 | Invited Tutorial: FPGA Hardware Security for Datacenters and Beyond. | Kaspar Matas, Tuan La, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch |
| 2020 | DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs. | Unai Martinez-Corral, Guillermo Callaghan, Konstantinos Iordanou, Cosmin Gorgovan, Koldo Basterretxea, Mikel Lujn |
| 2020 | Unleashing the Power of FPGAs as Programmable Switches. | Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois |