| 2020 | Cycle-Free FPGA Routing Graphs. | Ang Li, David Wentzlaff |
| 2020 | Maximizing CNN Throughput on FPGA Clusters. | Ruihao Li, Ke Liu, Mengying Zhao, Zhaoyan Shen, Xiaojun Cai, Zhiping Jia |
| 2020 | Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis. | Johannes de Fine Licht, Grzegorz Kwasniewski, Torsten Hoefler |
| 2020 | HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. | Jiajie Li, Yuze Chi, Jason Cong |
| 2020 | Establishing Trust in Microelectronics. | Lee W. Lerner |
| 2020 | High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA. | Martin Langhammer, Sergey Gribok, Gregg Baeckler |
| 2020 | Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA. | Atsushi Koshiba, Kouki Watanabe, Takaaki Miyajima, Kentaro Sano |
| 2020 | Multi-tenant FPGA Security: Challenges and Opportunities. | Patrick Koeberl |
| 2020 | Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography Algorithms. | Changsu Kim, Yongwoo Lee, Shinnung Jeong, Wen Wang, Jakub Szefer, Hanjun Kim |
| 2020 | V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. | Taesu Kim, Daehyun Ahn, Jae-Joon Kim |
| 2020 | Xilinx Vitis Unified Software Platform. | Vinod Kathail |
| 2020 | Buffer Placement and Sizing for High-Performance Dataflow Circuits. | Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella |
| 2020 | Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. | Lana Josipovic, Andrea Guerrieri, Paolo Ienne |
| 2020 | Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs. | Jiantong Jiang, Zeke Wang, Xue Liu, Juan Gmez-Luna, Nan Guan, Qingxu Deng, Wei Zhang, Onur Mutlu |
| 2020 | Symbiosis in Action: Reconfigurable Architectures and EDA. | Mahesh A. Iyer |
| 2020 | INTB: A New FPGA Interconnect Model for Architecture Exploration. | Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai |
| 2020 | BiS-KM: Enabling Any-Precision K-Means on FPGAs. | Zhenhao He, Zeke Wang, Gustavo Alonso |
| 2020 | Finding and Understanding Bugs in FPGA Synthesis Tools. | Yann Herklotz, John Wickerson |
| 2020 | FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10. | Ke He, Bo Liu, Yu Zhang, Andrew Ling, Dian Gu |
| 2020 | HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs. | Mathew Hall, Vaughn Betz |
| 2020 | Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. | Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong |
| 2020 | MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. | Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia |
| 2020 | Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. | Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic |
| 2020 | DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils. | Juan Escobedo, Mingjie Lin |
| 2020 | Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. | Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar |