| 2020 | Programming Abstractions for Configurable Hardware: Survey and Research Directions. | Samuel Dewan, Paulo Garcia |
| 2020 | Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. | Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka |
| 2020 | Architectural Enhancements in Intel Agilex™ FPGAs. | Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov |
| 2020 | FPGA-Accelerated Samplesort for Large Data Sets. | Han Chen, Sergey Madaminov, Michael Ferdman, Peter A. Milder |
| 2020 | Combining Dynamic & Static Scheduling in High-level Synthesis. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson |
| 2020 | CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time. | Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong |
| 2020 | Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. | Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle |
| 2020 | Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. | Endri Bezati, Mahyar Emami, James R. Larus |
| 2020 | StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging. | Sameh Attia, Vaughn Betz |
| 2020 | The Case for Hard Matrix Multiplier Blocks in an FPGA. | Aman Arora, Zhigang Wei, Lizy K. John |
| 2020 | Near-memory Acceleration for Scalable Phylogenetic Inference. | Nikolaos Alachiotis, Panagiotis Skrimponis, Emmanouil Pissadakis, Sundeep Rangan, Dionisios N. Pnevmatikatos |
| 2020 | Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators. | Tanvir Ahmed, Johannes Maximilian Khn |
| 2020 | Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search. | Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane |
| 2020 | AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. | Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin |
| 2019 | MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement. | Yun Zhou, Dries Vercruyce, Dirk Stroobandt |
| 2019 | Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization. | Jialiang Zhang, Jing Li |
| 2019 | Engaging Heterogeneous FPGAs in the Cloud. | Ke Zhang, Yisong Chang, Mingyu Chen, Yungang Bao, Zhiwei Xu |
| 2019 | A Fine-Grained Sparse Accelerator for Multi-Precision DNN. | Shulin Zeng, Yujun Lin, Shuang Liang, Junlong Kang, Dongliang Xie, Yi Shan, Song Han, Yu Wang, Huazhong Yang |
| 2019 | HSC-FPGA. | Ramtin Zand, Ronald F. DeMara |
| 2019 | A Reconfigurable Accelerator for Sparse Convolutional Neural Networks. | Weijie You, Chang Wu |
| 2019 | Constructing Concurrent Data Structures on FPGA with Channels. | Hui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei |
| 2019 | SwitchAgg: A Further Step Towards In-Network Computation. | Fan Yang, Zhan Wang, Xiaoxiao Ma, Guojun Yuan, Xuejun An |
| 2019 | Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. | Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer |
| 2019 | DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators. | Yu Xing, Shuang Liang, Lingzhi Sui, Zhen Zhang, Jiantao Qiu, Xijie Jia, Xin Liu, Yushun Wang, Yi Shan, Yu Wang |
| 2019 | Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. | Jiafeng Xie, Chiou-Yng Lee |