| 2003 | Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. | Matteo Sonza Reorda, Massimo Violante |
| 2003 | Design and Implementation of RNS-Based Adaptive Filters. | Javier Ramrez, Uwe Meyer-Bse, Antonio Garca, Antonio Lloris-Ruz |
| 2003 | Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. | Guillermo Pay Vay, Marcos Martnez Peir, Francisco Jos Ballester-Merelo, Francisco Jos Mora Mas |
| 2003 | An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors. | Stavros Paschalakis, Peter Lee, Miroslaw Bober |
| 2003 | Fault Simulation Using Partially Reconfigurable Hardware. | Abilio Parreira, Joo Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, Jos T. de Sousa |
| 2003 | Compiling for the Molen Programming Paradigm. | Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis |
| 2003 | Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. | Yasunori Osana, Tomonori Fukushima, Hideharu Amano |
| 2003 | A Study on the Design of Floating-Point Functions in FPGAs. | Fernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather |
| 2003 | FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition. | Eva M. Ortigosa, Pilar Martnez Ortigosa, Antonio Caas, Eduardo Ros, Rodrigo Ags, Julio Ortega |
| 2003 | A VHDL Library to Analyse Fault Tolerant Techniques. | Pilar Martnez Ortigosa, O. Lpez, R. Estrada, Inmaculada Garca, Ester M. Garzn |
| 2003 | Improving DSP Performance with a Small Amount of Field Programmable Logic. | John Y. Oliver, Venkatesh Akella |
| 2003 | Project of IPv6 Router with FPGA Hardware Accelerator. | Jiri Novotn, Otto Fuck, David Antos |
| 2003 | FPGA-Based Hardware/Software CoDesign of an Expert System Shell. | Aurel Netin, Dumitru Roman, Octavian Cret, Kalman Pusztai, Lucia Vacariu |
| 2003 | FPGA Implementation of a Maze Routing Accelerator. | John A. Nestor |
| 2003 | Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. | Tudor Murgan, Mihail Petrov, Alberto Garca Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard lkrug, Jrg Brakensiek |
| 2003 | An Algorithm Designer's Workbench for Platform FPGA's. | Sumit Mohanty, Viktor K. Prasanna |
| 2003 | A Real-Time Stereo Vision System with FPGA. | Yosuke Miyajima, Tsutomu Maruyama |
| 2003 | Switch Level Fault Emulation. | Seyed Ghassem Miremadi, Ali Reza Ejlali |
| 2003 | An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers. | Allen Michalski, Kris Gaj, Tarek A. El-Ghazawi |
| 2003 | ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. | Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins |
| 2003 | Very High Speed 17 Gbps SHACAL Encryption Architecture. | Mire McLoone, John V. McCanny |
| 2003 | Quark Routing. | Sean T. McCulloch, James P. Cohoon |
| 2003 | Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. | Brendan McAllister, Sakir Sezer, Ciaran Toal |
| 2003 | FPGA Processor for Real-Time Optical Flow Computation. | Selene Maya-Rueda, Miguel O. Arias-Estrada |
| 2003 | A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications. | Maurizio Martina, Andrea Molino, Federico Quaglio, Fabrizio Vacca |