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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2003Design of a Power Conscious, Customizable CDMA Receiver.Maurizio Martina, Andrea Molino, Mario Nicola, Fabrizio Vacca
2003DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.Jos Marn-Roig, Vicente Torres-Carot, Ma Jos Canet, Asuncion Perez-Pascual, Trinidad Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat
2003Networks on Chip as Hardware Components of an OS for Reconfigurable Systems.Thodore Marescaux, Jean-Yves Mignolet, T. Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins
2003Implementation of HW$im - A Real-Time Configurable Cache Simulator.Shih-Lien Lu, Konrad Lai
2003Reconfigurable Hybrid Architecture for Web Applications.David Rodrguez Lozano, Juan Manuel Snchez-Prez, Juan Antonio Gmez Pulido
2003Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications.Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Snchez-Reillo
2003An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall.John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim
2003Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware.Shaomeng Li, Jim Trresen, Oddvar Srsen
2003MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping.Miroslav Lcko, Jan Schier, Milan Tich, Markus Khl
2003A Model for Hardware Realization of Kernel Loops.Jirong Liao, Weng-Fai Wong, Tulika Mitra
2003Irregular Reconfigurable CAM Structures for Firewall Applications.T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
2003Building Run-Time Reconfigurable Systems from Tiles.Gareth Lee, George J. Milne
2003Non-uniform Segmentation for Hardware Function Evaluation.Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA.Barry Lee, Neil Burgess
2003Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications.Jess Lzaro, Jagoba Arias, Jos Luis Martn, Carlos Cuadrado
2003Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.Eryk Laskowski, Marek S. Tudruj
2003Arbitrating Instructions in an pmu-Coded CCM.Georgi Kuzmanov, Stamatis Vassiliadis
2003Testable Clock Routing Architecture for Field Programmable Gate Arrays.L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
2003Designing, Scheduling, and Allocating Flexible Arithmetic Components.Vinu Vijay Kumar, John C. Lach
2003Encoded-Low Swing Technique for Ultra Low Power Interconnect.Rohini Krishnan, Jos Pineda de Gyvez, Harry J. M. Veendrick
2003Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices.Andrzej Krasniewski
2003Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit
2003A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA.Tomoyoshi Kobori, Tsutomu Maruyama
2003Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo
2003Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking.Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
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