Field Programmable Logic and Applications
FPL
B
CORE rank
CORE rank (raw)
B
Fields of research
Computer Systems Engineering
Papers indexed
3,233
1994–2025
Papers per year
1994182 peak2025
Most published authors
FPL papers
3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2020 | RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms. | Niansong Zhang, Xiang Chen, Nachiket Kapre |
| 2020 | FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering Application. | Wei Yan, Fatemeh Tehranipoor, Xuan Zhang, John A. Chandy |
| 2020 | A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. | Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang |
| 2020 | Secret Sharing MPC on FPGAs in the Datacenter. | Pierre-Francois Wolfe, Rushi Patel, Robert Munafo, Mayank Varia, Martin C. Herbordt |
| 2020 | Caffe Barista: Brewing Caffe with FPGAs in the Training Loop. | Diederik Adriaan Vink, Aditya Rajagopal, Stylianos I. Venieris, Christos-Savvas Bouganis |
| 2020 | LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications. | Yaman Umuroglu, Yash Akhauri, Nicholas James Fraser, Michaela Blott |
| 2020 | TTA-SIMD Soft Core Processors. | Kati Tervo, Samawat Malik, Topi Leppnen, Pekka Jskelinen |
| 2020 | Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware. | Frans Skarman, Oscar Gustafsson, Daniel Jung, Mattias Krysander |
| 2020 | NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling. | Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gmez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal |
| 2020 | FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. | Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini |
| 2020 | Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. | Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye |
| 2020 | Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES. | Joo Carlos Resende, Ricardo J. R. Mas, Ricardo Chaves |
| 2020 | Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAs. | Arjun Ramaswami, Tobias Kenter, Thomas D. Khne, Christian Plessl |
| 2020 | Precise Pointer Analysis in High-Level Synthesis. | Nadesh Ramanathan, George A. Constantinides, John Wickerson |
| 2020 | FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction. | Linjun Qiao, Guojie Luo, Wentai Zhang, Ming Jiang |
| 2020 | Power Wasting Circuits for Cloud FPGA Attacks. | George Provelengios, Daniel E. Holcomb, Russell Tessier |
| 2020 | Using DSP Slices as Content-Addressable Update Queues. | Thomas B. Preuer, Monica Chiosa, Alexander Weiss, Gustavo Alonso |
| 2020 | Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge. | Duvindu Piyasena, Miyuru Thathsara, Sathursan Kanagarajah, Siew Kei Lam, Meiqing Wu |
| 2020 | A Self-Compilation Flow Demo on FOS - The FPGA Operating System. | Khoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch |
| 2020 | An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. | Philippos Papaphilippou, Chris Brooks, Wayne Luk |
| 2020 | A Configurable TLB Hierarchy for the RISC-V Architecture. | Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos |
| 2020 | Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency. | Erhan Baturay Onural, Ismail Emir Yuksel, Behzad Salami |
| 2020 | Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2020 | Partial Reconfiguration for Design Optimization. | Marie Nguyen, Nathan Serafin, James C. Hoe |
| 2020 | A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. | Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada |
326–350 of 3,233← PreviousNext →
Comparable venues
Other A*/A conferences filed under the same field of research.
- ADATEDesign, Automation and Test in Europe Conference
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- AITCIEEE International Test Conference
- A*ISCAACM International Symposium on Computer Architecture
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design