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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2018SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing.Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
2018An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs.Thiem Van Chu, Kenji Kise
2018FPGASwarm: High Throughput Model Checking on FPGAs.Shenghsun Cho, Michael Ferdman, Peter A. Milder
2018An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics.Georgios Chatzianastasiou, George A. Constantinides
2018Digital Pre-distortion Implemented Using FPGA.Declan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley
2018Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions.Lake Bu, Michel A. Kinsy
2018Towards in the Field Fast Pathogens Detection Using FPGAs.Simone Casale Brunet, Thierry Schpbach, Nicolas Guex, Christian Iseli, Alan J. Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati
2018Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs.Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2018A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation.Michael Barrow, Steven M. Burns, Ryan Kastner
2018Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.Sam Amiri, Mohammad Hosseinabady, Andrs Rodrguez, Rafael Asenjo, Angeles G. Navarro, Jos L. Nez-Yez
2018Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip.Tobias Alonso, Mario Ruiz, Angel Lopez Garcia-Arias, Gustavo Sutter, Jorge E. Lpez de Vergara
2018Accelerated Inference of Positive Selection on Whole Genomes.Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos, Dionisios N. Pnevmatikatos
2018Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs.Ibrahim Ahmed, Shuze Zhao, James Meijers, Olivier Trescases, Vaughn Betz
2018Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories.Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon
2018DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
2018Latency Insensitive Design Styles for FPGAs.Mustafa Abbas, Vaughn Betz
2018Lightweight Secure Processor Prototype on FPGA.Yao Liu, Ray C. C. Cheung, Hei Wong
2018A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs.Behzad Salami, Osman S. nsal, Adrin Cristal
2018Fault Characterization Through FPGA Undervolting.Behzad Salami, Osman S. Unsal, Adrin Cristal
2017High-performance video content recognition with long-term recurrent convolutional network for FPGA.Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen
2017Evaluating FPGA clusters under wide ranges of design parameters.Grace Zgheib, Paolo Ienne
2017Quantifying and mitigating the costs of FPGA virtualization.Sadegh Yazdanshenas, Vaughn Betz
2017Phase calibrated ring oscillator PUF design and implementation on FPGAs.Wei Yan, Chenglu Jin, Fatemeh Tehranipoor, John A. Chandy
2017REAPR: Reconfigurable engine for automata processing.Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron, Mircea Stan
2017Parallel RRT∗ architecture design for motion planning.Size Xiao, Neil Bergmann, Adam Postula
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