| 2017 | An implementation of list successive cancellation decoder with large list size for polar codes. | ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, ChongYang Zeng, Jie Jin, Bin Li |
| 2017 | A high-throughput reconfigurable processing array for neural networks. | Ephrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho |
| 2017 | A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs. | Alexander Wild, Georg T. Becker, Tim Gneysu |
| 2017 | Transparent memory encryption and authentication. | Mario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard |
| 2017 | FPGA acceleration of multilevel ORB feature extraction for computer vision. | Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond |
| 2017 | ARMHEx: A framework for efficient DIFT in real-world SoCs. | Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat |
| 2017 | ARMHEx: A hardware extension for DIFT on ARM-based SoCs. | Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat |
| 2017 | Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs. | Kizheppatt Vipin, Jan Gray, Nachiket Kapre |
| 2017 | Parallel dot-products for deep learning on FPGA. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2017 | Latency-driven design for FPGA-based convolutional neural networks. | Stylianos I. Venieris, Christos-Savvas Bouganis |
| 2017 | A security library for FPGA interlays. | Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch |
| 2017 | Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. | Yohann Uguen, Florent de Dinechin, Steven Derrien |
| 2017 | Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. | Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano |
| 2017 | Vivado design interface: An export/import capability for Vivado FPGA designs. | Thomas Townsend, Brent E. Nelson |
| 2017 | Validating optimisations for chaotic simulations. | James Stanley Targett, Peter D. Dben, Wayne Luk |
| 2017 | Heterogeneous virtualized network function framework for the data center. | Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow |
| 2017 | FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai |
| 2017 | Parallel FPGA routing: Survey and challenges. | Mirjana Stojilovic |
| 2017 | Demonstration of a partial reconfiguration based microphone array network emulator. | Bruno da Silva, Federico Domnguez, An Braeken, Abdellah Touhafi |
| 2017 | A partial reconfiguration based microphone array network emulator. | Bruno da Silva, Federico Domnguez, An Braeken, Abdellah Touhafi |
| 2017 | doppioDB: A hardware accelerated database. | David Sidler, Muhsen Owaida, Zsolt Istvn, Kaan Kara, Gustavo Alonso |
| 2017 | HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics. | Jiayi Sheng, Chen Yang, Ahmed Sanaullah, Michael Papamichael, Adrian M. Caulfield, Martin C. Herbordt |
| 2017 | Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation. | Shengjia Shao, Wayne Luk |
| 2017 | Dynamic bitwidth assignment for efficient dot products. | Simon Joel Schmidt, David Boland |
| 2017 | The Monte Carlo PUF. | Vladimir Rozic, Bohan Yang, Jo Vliegen, Nele Mentens, Ingrid Verbauwhede |