| 2017 | A generic high throughput architecture for stream processing. | Christos Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos |
| 2017 | Optimizing streaming stencil time-step designs via FPGA floorplanning. | Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio |
| 2017 | FPGA acceleration of the scoring process of X!TANDEM for protein identification. | Jin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang |
| 2017 | Accelerated analysis of Boolean gene regulatory networks. | Mitra Purandare, Raphael Polig, Christoph Hagleitner |
| 2017 | Scalable high-performance architecture for convolutional ternary neural networks on FPGA. | Adrien Prost-Boucle, Alban Bourge, Frdric Ptrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy |
| 2017 | Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs. | Thomas B. Preuer |
| 2017 | DFiant: A dataflow hardware description language. | Oron Port, Yoav Etsion |
| 2017 | Evaluating high-level design strategies on FPGAs for high-performance computing. | Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka |
| 2017 | Evaluating high-level design strategies on FPGAs for high-performance computing. | Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka |
| 2017 | A programming model and runtime system for approximation-aware heterogeneous computing. | Ioannis Parnassos, Nikolaos Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Athanasios Gkaras, Konstantinos Kanellis, Christos D. Antonopoulos, Michalis Spyrou, Manolis Maroudas |
| 2017 | Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms. | Muhsen Owaida, Hantian Zhang, Ce Zhang, Gustavo Alonso |
| 2017 | Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. | Jose Raul Garcia Ordaz, Dirk Koch |
| 2017 | Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices. | Stephan Nolting, Lin Liu, Guillermo Pay-Vay |
| 2017 | Application-specific soft-core vector processor for advanced driver assistance systems. | Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Pay-Vay |
| 2017 | Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. | Ho-Cheung Ng, Shuanglong Liu, Wayne Luk |
| 2017 | Dynamic power estimation based on switching activity propagation. | Yehya Nasser, Jean-Christophe Prvotet, M. Heiard, Jordane Lorandel |
| 2017 | FISH: Linux system calls for FPGA accelerators. | Kevin Nam, Blair Fort, Stephen Brown |
| 2017 | A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. | Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato |
| 2017 | A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. | Hiroki Nakahara, Tomoya Fujii, Shimpei Sato |
| 2017 | High performance binary neural networks on the Xeon+FPGA™ platform. | Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong |
| 2017 | Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs. | Yifeng Mo, Shuguo Li |
| 2017 | In-switch approximate processing: Delayed tasks management for MapReduce applications. | Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
| 2017 | VineTalk: Simplifying software access and sharing of FPGAs in datacenters. | Stelios Mavridis, Emmanouil Pavlidakis, Ioannis Stamoulias, Christos Kozanitis, Nikolaos Chrysos, Christoforos Kachris, Dimitrios Soudris, Angelos Bilas |
| 2017 | TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features. | Eric Matthews, Lesley Shannon |
| 2017 | Area-optimized montgomery multiplication on IGLOO 2 FPGAs. | Pedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens |