| 2017 | An implementation method of poisson image editing on FPGA. | Ryouhei Maeda, Tsutomu Maruyama |
| 2017 | An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. | Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo |
| 2017 | Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. | Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello |
| 2017 | Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. | Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li |
| 2017 | K-means clustering on CGRA. | Joo D. Lopes, Jos T. de Sousa, Horcio C. Neto, Mrio P. Vstias |
| 2017 | Tile size selection for optimized memory reuse in high-level synthesis. | Junyi Liu, John Wickerson, George A. Constantinides |
| 2017 | Learning-based interconnect-aware dataflow accelerator optimization. | Shuangnan Liu, Benjamin Carrin Schfer |
| 2017 | Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. | Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch |
| 2017 | Decision tree based hardware power monitoring for run time dynamic power management in FPGA. | Zhe Lin, Wei Zhang, Sharad Sinha |
| 2017 | High throughput AES encryption/decryption with efficient reordering and merging techniques. | Lijuan Li, Shuguo Li |
| 2017 | High-quality view interpolation based on depth maps and its hardware implementation. | Yanzhe Li, Kai Huang, Luc Claesen |
| 2017 | PAAS: A system level simulator for heterogeneous computing architectures. | Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang |
| 2017 | Body bias optimization for variable pipelined CGRA. | Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano |
| 2017 | Flexible FPGA design for FDTD using OpenCL. | Tobias Kenter, Jens Frstner, Christian Plessl |
| 2017 | Mapping of P4 match action tables to FPGA. | Michal Kekely, Jan Korenek |
| 2017 | Deflection-routed butterfly fat trees on FPGAs. | Nachiket Kapre |
| 2017 | Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs. | Lester Kalms, Diana Ghringer |
| 2017 | FPGA acceleration of spark applications in a Pynq cluster. | Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris |
| 2017 | Accelerating low bit-width convolutional neural networks with embedded FPGA. | Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang |
| 2017 | A dynamic partial reconfigurable overlay concept for PYNQ. | Benedikt Janen, Pascal Zimprich, Michael Hbner |
| 2017 | Rapid implementation of a partially reconfigurable video system with PYNQ. | Brad L. Hutchings, Michael J. Wirthlin |
| 2017 | A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. | Mohammad Hosseinabady, Jos Luis Nez-Yez |
| 2017 | Exploring the potential of reconfigurable platforms for order book update. | Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang |
| 2017 | Shielding non-trusted IPs in SoCs. | Festus Hategekimana, Taylor J. L. Whitaker, Md Jubaer Hossain Pantho, Christophe Bobda |
| 2017 | Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo. | David J. Greaves |