| 2016 | High-speed PCAP configuration scrubbing on Zynq-7000 All Programmable SoCs. | Aaron Stoddard, Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin |
| 2016 | Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures. | Srikanth Sridharan, Paolo Durante, Christian Faerber, Niko Neufeld |
| 2016 | Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer. | William Andrew Simon, Ahmet Caner Yuzuguler, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli |
| 2016 | A runtime reconfigurable FPGA-based microphone array for sound source localization. | Bruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi |
| 2016 | Runtime reconfigurable beamforming architecture for real-time sound-source localization. | Bruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi |
| 2016 | Low-latency TCP/IP stack for data center applications. | David Sidler, Zsolt Istvn, Gustavo Alonso |
| 2016 | Overcoming resource underutilization in spatial CNN accelerators. | Yongming Shen, Michael Ferdman, Peter A. Milder |
| 2016 | Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. | Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski |
| 2016 | Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams. | Ismail San, Nicole Fern, etin Kaya Ko, Kwang-Ting Cheng |
| 2016 | Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. | Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio Lpez-Buedo, Jorge E. Lpez de Vergara, C. Sisterna |
| 2016 | Improved resource sharing for FPGA DSP blocks. | Bajaj Ronak, Suhaib A. Fahmy |
| 2016 | High-level synthesis for medical image processing on Systems on Chip: A case study. | Fraser D. Robinson, Louise H. Crockett, William H. Nailon, Robert W. Stewart |
| 2016 | Controller architecture for low-latency access to phase-change memory in OpenPOWER systems. | Antonios Prodromakis, Nikolaos Papandreou, Eleni Bougioukou, Urs Egger, Nikos Toulgaridis, Theodore Antonakopoulos, Haralampos Pozidis, Evangelos Eleftheriou |
| 2016 | Annotation-based finite-state transducers on reconfigurable devices. | Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama |
| 2016 | A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices. | Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, Lilian Bossuet |
| 2016 | Fast hierarchical NPN classification. | Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko |
| 2016 | The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer. | Oleg Petelin, Vaughn Betz |
| 2016 | SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip. | Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas |
| 2016 | FPGA-based accelerator design from a domain-specific language. | M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2016 | Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. | Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr |
| 2016 | EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits. | Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk |
| 2016 | XNoC: A non-intrusive TDM circuit-switched Network-on-Chip. | Tuan D. A. Nguyen, Akash Kumar |
| 2016 | Efficient processing of phased array radar in sense and avoid application using heterogeneous computing. | Luke Newmeyer, Doran Wilde, Brent E. Nelson, Michael J. Wirthlin |
| 2016 | Modelling delay degradation due to NBTI in FPGA Look-up tables. | Mohammad Naouss, Franois Marc |
| 2016 | Architectural exploration and implementation of an image processing chain with SpaceStudio | Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier |