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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2016Body bias grain size exploration for a coarse grained reconfigurable accelerator.Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2016Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2016A hardware/software codesign framework for vision-based ADAS.Leandro Andrade Martinez, Eduardo Marques
2016Reconfigurable circuit for implementation of family of 4-phase latch protocols.Jotham Vaddaboina Manoranjan, Kenneth S. Stevens
2016Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons.Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre
2016Optimizing hardware design for Human Action Recognition.Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury
2016TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs.Weina Lu, Yu Hu, Jing Ye, Xiaowei Li
2016Model-based optimization of High Level Synthesis directives.Charles Lo, Paul Chow
2016Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs.Dong Liu, Benjamin Carrin Schfer
2016Approximate Frequent Itemset Mining for streaming data on FPGA.Yubin Li, Yuliang Sun, Guohao Dai, Qiang Xu, Yu Wang, Huazhong Yang
2016SoC and FPGA oriented high-quality stereo vision system.Yanzhe Li, Kai Huang, Luc Claesen
2016A high performance FPGA-based accelerator for large-scale convolutional neural networks.Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang
2016Memory efficient and high performance key-value store on FPGA using Cuckoo hashing.Wei Liang, Wenbo Yin, Ping Kang, Lingli Wang
2016Efficient sum of absolute difference computation on FPGAs.Martin Kumm, Marco Kleinlein, Peter Zipf
2016An FPGA-based high-throughput stream join architecture.Charalabos Kritikakis, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos
2016An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures.Farheen Fatima Khan, Andy Gean Ye
2016Stress-aware routing to mitigate aging effects in SRAM-based FPGAs.Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jrg Henkel, Hossein Asadi
2016Fast and robust hashing for database operators.Kaan Kara, Gustavo Alonso
2016Survey of domain-specific languages for FPGA computing.Nachiket Kapre, Samuel Bayliss
2016AdapNoC: A fast and flexible FPGA-based NoC simulator.Hadi Mardani Kamali, Shaahin Hessabi
2016Fast and area efficient adder for wide data in recent Xilinx FPGAs.Petter Kallstrom, Oscar Gustafsson
2016A survey on reconfigurable accelerators for cloud computing.Christoforos Kachris, Dimitrios Soudris
2016SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA.Xijie Jia, Kaiyuan Guo, Wenqiang Wang, Yu Wang, Huazhong Yang
2016Preface.Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016Effects of I/O routing through column interfaces in embedded FPGA fabrics.Christophe Huriaux, Olivier Sentieys, Russell Tessier
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