Field Programmable Logic and Applications

FPL

CORE rank

CORE rank (raw)

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Best Computer Systems Engineering conferences

Papers per year

1994182 peak2025

Most published authors

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

Year	Title	Authors
2017	Find the real speed limit: FPGA CAD for chip-specific application delay measurement.	Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz
2017	A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN.	Robin Aggleton, Luis E. Ardila-Perez, Fionn Amhairghen Ball, Matthias Norbert Balzer, James John Brooke, Luigi Calligaris, Michele Caselle, Davide Cieri, Emyr John Clement, Geoffrey Hall, Kristian Harder, Peter R. Hobson, Gregory M. Iles, Thomas James, Konstantinos Manolopoulos, Takashi Matsushita, Alexander D. Morton, David Newbold, Sudarshan Paramesvaran, Mark Franco Pesaresi, Ivan D. Reid, Andrew W. Rose, Oliver Sander, Thomas Schuh, Claire Shepherd-Themistocleous, Antoni Shtipliyski, Sioni Paris Summers, Alexander D. Tapper, Ian Tomalin, Kirika Uchida, Paschalis Vichoudis, Marc Weber
2017	FPGA-based design of a self-checking TMR voter.	Umar Afzaal, Jeong-A Lee
2017	Relocation-aware communication network for circuits on Xilinx FPGAs.	Adewale Adetomi, Godwin Enemali, Tughrul Arslan
2016	Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules.	Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk
2016	Single-FPGA 3D ultrasound beamformer.	Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2016	Boosting convergence of timing closure using feature selection in a Learning-driven approach.	Que Yanghua, Harnhua Ng, Nachiket Kapre
2016	Optimal random sampling based path planning on FPGAs.	Size Xiao, Adam Postula, Neil W. Bergmann
2016	A partial reconfiguration controller for Altera Stratix V FPGAs.	Zhenzhong Xiao, Dirk Koch, Mikel Lujn
2016	Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs.	Jori Winderickx, Joan Daemen, Nele Mentens
2016	Demonstration of a context-switch method for heterogeneous reconfigurable systems.	Arief Wicaksana, Alban Bourge, Olivier Muller, Frdric Rousseau
2016	Relational query processing on OpenCL-based FPGAs.	Zeke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang
2016	An implementation method of the box filter on FPGA.	Sichao Wang, Tsutomu Maruyama
2016	Towards a hardware-assisted information flow tracking ecosystem for ARM processors.	Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat
2016	Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.	Shrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb
2016	Packet processing on FPGA SoC with DPDK.	Jan Viktorin, Jan Korenek
2016	JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication.	Malte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy
2016	Runtime-quality tradeoff in partitioning based multithreaded packing.	Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
2016	Search-based synthesis of approximate circuits implemented into FPGAs.	Zdenek Vascek, Luks Sekanina
2016	Liquid: Fast placement prototyping through steepest gradient descent movement.	Elias Vansteenkiste, Seppe Lenders, Dirk Stroobandt
2016	Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization.	Burak Unal, Ali Akoglu
2016	Hardware acceleration of feature detection and description algorithms on low-power embedded platforms.	Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar
2016	Hardware acceleration of a software-based VPN.	Furkan Turan, Ruan de Clercq, Pieter Maene, Oscar Reparaz, Ingrid Verbauwhede
2016	An XDL alternative for interfacing RapidSmith and Vivado.	Thomas Townsend, Brent E. Nelson, Michael J. Wirthlin
2016	A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.	Daisuke Suzuki, Takahiro Hanyu

651–675 of 3,233← Previous Next →

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