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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2012CRUSH: Cognitive Radio Universal Software Hardware.George Eichinger, Kaushik R. Chowdhury, Miriam Leeser
2012FPGAs for trusted cloud computing.Ken Eguro, Ramarathnam Venkatesan
2012High-level linear projection circuit design optimization framework for FPGAs under over-clocking.Rui Policarpo Duarte, Christos-Savvas Bouganis
2012Deep-pipelined FPGA implementation of ellipse estimation for eye tracking.Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri
2012SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration.Florian Devic, Lionel Torres, Jrmie Crenne, Benot Badrignans, Pascal Benoit
2012An efficient hardware architecture of the optimised SIFT descriptor generation.Wenjuan Deng, Yiqun Zhu, Hao Feng, Zhiguo Jiang
2012Raising the abstraction level of HDL for control-dominant applications.Marc-Andr Daigneault, Jean-Pierre David
2012From opencl to high-performance hardware on FPGAS.Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh
2012Dual MicroBlaze rekeying processor for group key management.Jos M. Granado Criado, Miguel A. Vega-Rodrguez, Juan Manuel Snchez-Prez, Juan Antonio Gmez Pulido
2012Lightweight reconfiguration security services for AXI-based MPSoCs.Pascal Cotret, Guy Gogniat, Jean-Philippe Diguet, Jrmie Crenne
2012Fast digital rendering for special effects.Sam Collinson, John Morris
2012A scalable FPGA-based design for field programmable large-scale ion channel simulations.Graeme Coapes, Terrence S. T. Mak, Junwen Luo, Alex Yakovlev, Chi-Sang Poon
2012Low area memory-free FPGA implementation of the AES algorithm.Junfeng Chu, Mohammed Benaissa
2012Hardware implementation of MRF map inference on an FPGA platform.Jungwook Choi, Rob A. Rutenbar
2012Non-volatile 3D stacking RRAM-based FPGA.Yi-Chung Chen, Wenhua Wang, Hai Li, Wei Zhang
2012An FPGA aligner for short read mapping.Yupeng Chen, Bertil Schmidt, Douglas L. Maskell
2012Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering.Doris Chen, Deshanand P. Singh
2012Adaptive Sequential Monte Carlo approach for real-time applications.Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski
2012Hardware implementation of motion blur removal.Thusitha N. Chandrapala, Amila P. Cabral, Sapumal Ahangama, Thilina S. Ambagahawaththa, Jayathu G. Samarawickrama
2012Automating the design of mLUT MPSoPC FPGAs in the cloud.Eugene Cartwright, Azad Fahkari, Sen Ma, Christina Smith, Miaoqing Huang, David Andrews, Jason Agron
2012Design and utilization of an FPGA cluster to implement a Digital Wireless Channel Emulator.Scott Buscemi, Ron Sass
2012An open-source design and validation platform for reconfigurable systems.Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio
2012Speedy bus mastering PCI express.Ray Bittner
2012Real-time corner and polygon detection system on FPGA.Chunmeng Bi, Tsutomu Maruyama
2012Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study.Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
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