| 2010 | Real-Time Classification of Multimedia Traffic Using FPGA. | Weirong Jiang, Maya B. Gokhale |
| 2010 | Test Compression for Dynamically Reconfigurable Processors. | Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Koichiro Furuta |
| 2010 | Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. | Antonin Hermanek, Michal Kunes, Milan Tich |
| 2010 | A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor. | Gerald Hempel, Christian Hochberger, Andreas Koch |
| 2010 | Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications. | Deborah Goshorn, Junguk Cho, Ryan Kastner, Shahnam Mirzaei |
| 2010 | A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. | Heiner Giefers, Marco Platzner |
| 2010 | Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters. | Amir Hossein Gholamipour, Fadi J. Kurdahi, Ahmed M. Eltawil, Mazen A. R. Saghir |
| 2010 | Finding System-Level Information and Analyzing Its Correlation to FPGA Placement. | Farnaz Gharibian, Lesley Shannon, Peter Jamieson |
| 2010 | Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core. | Fabio Garzia, Waqar Hussain, Jari Nurmi |
| 2010 | A Reconfigurable Computing Scheduler Optimized for Multicore Systems. | Philip Garcia, Kyle Rupnow, Katherine Compton |
| 2010 | Automation Framework for Large-Scale Regular Expression Matching on FPGA. | Thilan Ganegedara, Yi-Hua E. Yang, Viktor K. Prasanna |
| 2010 | ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. | Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster |
| 2010 | A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation. | Hagen Gdke-Ltjens, Benjamin Thielmann, Andreas Koch |
| 2010 | A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks. | Wen-Hui Fu, Jun Jiang, Xi Qin, Ting Yi, Zhiliang Hong |
| 2010 | FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks. | Ricardo S. Ferreira, Julio C. Goldner Vendramini |
| 2010 | Erlang Inspired Hardware. | Paulo Ferreira, Joo Canas Ferreira, Jos Carlos Alves |
| 2010 | Exploration of Short Reads Genome Mapping in Hardware. | Edward Fernandez, Walid A. Najjar, Elena Yavorska Harris, Stefano Lonardi |
| 2010 | Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware. | Junfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Gneysu, Christof Paar, Ingrid Verbauwhede |
| 2010 | Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays. | Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck |
| 2010 | Customized Exposed Datapath Soft-Core Design Flow with Compiler Support. | Otto Esko, Pekka Jskelinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, Jos Ignacio Martnez |
| 2010 | Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration. | Stephanie Drzevitzky |
| 2010 | Reconfigurable Hardware for Power-over-Fiber Applications. | Michael Dreschmann, Michael Hbner, Moritz Rger, Oliver Sander, Christos Klamouris, Jrgen Becker, Wolfgang Freude, Juerg Leuthold |
| 2010 | Pipelined FPGA Adders. | Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca |
| 2010 | Multiplicative Square Root Algorithms for FPGAs. | Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy |
| 2010 | Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA. | Florian Devic, Lionel Torres, Benot Badrignans |