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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Towards a unique FPGA-based identification circuit using process variations.Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Mller, Manfred Glesner, Peter Zipf
2009Data parallel FPGA workloads: Software versus hardware.Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2009FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture.Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Feng-Hsiung Hsu
2009Compact FPGA implementation of Camellia.Panasayya Yalla, Jens-Peter Kaps
2009Self-organizing multi-cue fusion for FPGA-based embedded imaging.Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jrgen Teich
2009A radix-8 complex divider for FPGA implementation.Dong Wang, Milos D. Ercegovac, Nanning Zheng
2009Efficient techniques and methodologies for embedded system design usign free hardware and open standards.Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido
2009DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs.Rajesh Velegalati, Jens-Peter Kaps
2009FPGA-accelerated Information Retrieval: High-efficiency document filtering.Wim Vanderbauwhede, Leif Azzopardi, Mahmoud Moadeli
2009Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs.Maurizio Tranchero, Leonardo Maria Reyneri
2009Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm.David W. Thni, Alfred Strey
2009A novel states recovery technique for the TMR softcore processor.Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
2009Accelerating HMMER search using FPGA.Toyokazu Takagi, Tsutomu Maruyama
2009sFPGA2 - A scalable GALS FPGA architecture and design methodology.Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli
2009High speed fixed point dividers for FPGAs.Gustavo Sutter, Jean-Pierre Deschamps
2009A toolset for the analysis and optimization of motion estimation algorithms and processors.Trevor Spiteri, George Vafiadis, Jos Luis Nez-Yez
2009A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems.Joannis Sotiropoulos, Ioannis Papaefstathiou
2009Area estimation and optimisation of FPGA routing fabrics.Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2009Recursion in reconfigurable computing: A survey of implementation approaches.Iouliia Skliarova, Valery Sklyarov
2009A comparison of FPGA and FPAA technologies for a signal processing application.Roberto Selow, Heitor S. Lopes, Carlos Raimundo Erig Lima
2009Bitstream compression through frame removal and partial reconfiguration.Benjamin Sellers, Jonathan Heiner, Michael J. Wirthlin, Jeff Kalb
2009Compensating for variability in FPGAs by re-mapping and re-placement.N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
2009An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure.Tobias Schumacher, Christian Plessl, Marco Platzner
2009A runtime relocation based workflow for self dynamic reconfigurable systems design.Marco D. Santambrogio, Massimo Morandi, Marco Novati, Donatella Sciuto
2009Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
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