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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2009Compiler assisted runtime task scheduling on a reconfigurable computer.Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels
2009Performance metrics for hybrid multi-tasking systems.Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton
2009An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009Random numbers generation: Investigation of narrowtransitions suppression on FPGA.Vladimir Rozic, Ingrid Verbauwhede
2009The evolution of architecture exploration of programmable devices.Jonathan Rose
2009An FPGA design for evaluating score function in protein energy calculation.Jose Manuel Romero-Ximil, Arturo Daz-Prez
2009SVM speaker verification system based on a low-cost FPGA.Rafael Ramos-Lara, Mariano Lpez-Garca, Enrique F. Cant-Navarro, Luis Puente-Rodriguez
2009Hot-Swapping architecture extension for mitigation of permanent functional unit faults.Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
2009Reconfiguration-based time-to-digital converter for Virtex FPGAs.ngel Quirs-Olozbal, Juan Manuel Barrientos-Villar, Ma de los ngeles Cifredo Chacn
2009Mapping basic prefix computations to fast carry-chain structures.Thomas B. Preuer, Rainer G. Spallek
2009Noise impact of single-event upsets on an FPGA-based digital filter.Brian H. Pratt, Michael J. Wirthlin, Michael P. Caffrey, Paul S. Graham, Keith Morgan
2009Rapid design exploration framework for application-aware customization of soft core processors.Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan
2009Dynamic Polymorphic Reconfiguration for anti-tamper circuits.Roy Porter, Samuel J. Stone, Yong C. Kim, Jeffrey Todd McDonald, LaVern A. Starman
2009Enhancements to FPGA design methodology using streaming.Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2009Numerically controlled oscillators using linear approximation.Hans-Jrg Pfleiderer, Stefan Lachowicz
2009Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis.Hiren J. Patel, Yong C. Kim, Jeffrey Todd McDonald, LaVern A. Starman
2009Exploiting fast carry-chains of FPGAs for designing compressor trees.Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano
2009A reconfigurable FIR/FFT unit for wireless telecommunication systems.Maroun Ojail, Raphal David, Stphane Chevobbe, Didier Demigny
2009FPGA-accelerated retinal vessel-tree extraction.Alejandro Nieto, Vctor M. Brea, David Lpez Vilario
2009Clock duplicity for high-precision timestamping in Gigabit Ethernet.Carles Nicolau, Dolors Sala, Enrique Cant
2009In field, energy-performance tunable FPGA architectures.Bita Nezamfar, Mark Horowitz
2009A virus scanning engine using a parallel finite-input memory machine and MPUs.Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009Mems optically reconfigurable gate array.Hironobu Morita, Minoru Watanabe
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